CY8CTMG200-32LQXI Datasheet, PDF (285/309 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

SLP_CFG3
1,EDh
21.4.26 SLP_CFG3
Sleep Configuration Register 3
Individual Register Names and Addresses:
SLP_CFG3 : 1,EDh
7
Access : POR
Bit Name
6
RW : 1
DBL_TAPS
5
4
RW : 11
T2TAP[1:0]
1,EDh
3
2
RW : 11
T1TAP[1:0]
1
0
RW : 11
T0TAP[1:0]
This register holds the configuration of the wakeup sequence taps.
It is strongly recommended to not alter this register setting.
In the table above, note that the reserved bit is a grayed table cell and is not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the Register Definitions on
page 77 in the Sleep and Watchdog chapter.
Bit
Name
Description
6
DBL_TAPS
5:4
T2TAP[1:0]
3:2
T1TAP[1:0]
1:0
T0TAP[1:0]
When this bit is set all the tap values (T0, T1, and T2) are doubled for the wakeup sequence.
These bits control the duration of the T2-T4 sequence (see Figure 10-2 on page 75) by selecting a
tap from the WakeupTimer. Note: The T2 delay is only valid for the wakeup sequence. It is not used
for the buzz sequence.
00
1 µs
01
2 µs
10
5 µs
11
10 µs
These bits control the duration of the T1-T2 sequence (see Figure 10-2 on page 75) by selecting a
tap from the Wakeup Timer.
00
3 µs
01
4 µs
10
5 µs
11
10 µs
These bits control the duration of the T0-T1 sequence (see Figure 10-2 on page 75) by selecting a
tap from the Wakeup Timer.
00
10 µs
01
14 µs
10
20 µs
11
30 µs
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
285
[+] Feedback