CY8CTMG200-32LQXI Datasheet, PDF (106/309 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

Section D: System Resources
System Resources Register Summary
The table below lists all the registers for the system resources, in address order, within their system resource configuration.
The bits that are grayed out are reserved bits. If you write these bits, always write them with a value of ‘0’.
Summary Table of the System Resource Registers
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
DIGITAL CLOCK REGISTERS (page 112)
1,BDh
1,D1h
1,DDh
1,E0h
1,E2h
USB_MISC_C
R
OUT_P0
OUT_P1
OSC_CR0
OSC_CR2
P0P7D
P16D
X32ON
P0P7EN
P16EN
Disable Buzz
P0P4D
P14D
No Buzz
P0P4EN
P14EN
P12D
Sleep[1:0]
CLK48MEN
USB_SE_
EN
USB_ON
USB_CLK_
ON
P12EN P10D
P10EN
CPU Speed[2:0]
EXT-
CLKEN
IMODIS
RW : 0
RW : 00
RW : 00
RW : 01
RW : 0
I2C SLAVE REGISTERS (page 122)
0,C8h
0,C9h
0,CAh
0,CBh
0,CCh
0,CDh
0,CEh
0,CFh
0,D6h
0,D7h
0,D8h
I2C_XCFG
I2C_XSTAT
I2C_ADDR
I2C_BP
I2C_CP
CPU_BP
CPU_CP
I2C_BUF
I2C_CFG
I2C_SCR
I2C_DR
Bus Error
PSelect
Stop
Status
No BC Int
Buffer
Mode
Dir
Slave Address[6:0]
I2C Base Pointer[4:0]
I2C Current Pointer4:0]
CPU Base Pointer4:0]
CPU Current Pointer4:0]
Data Buffer[7:0]
Stop IE
Clock Rate[1:0]
ACK
Address Transmit LRB
Data[7:0]
HW Addr En RW : 0
Slave Busy
Enable
Byte
Complete
R: 0
RW : 00
R : 00
R : 00
RW: 00
R : 00
RW : 00
RW : 00
# : 00
RW : 00
SYSTEM RESET REGISTERS (page 137)
x,FEh
x,FFh
CPU_SCR1
CPU_SCR0
IRESS
GIES
WDRS
SLIMO[1:0]
PORS
Sleep
IRAMDIS
STOP
#:0
# : XX
POR REGISTERS (page 143)
1,E3h
1,E4h
VLT_CR
VLT_CMP
PORLEV[1:0]
LVDTBEN
VM[2:0]
NoWrite
POR_EXT LVD
RW : 00
R:#
SPI REGISTERS (page 147)
0,29h
0,2Ah
0,2Bh
1,29h
SPI_TXR
SPI_RXR
SPI_CR
SPI_CFG
LSb First
Overrun
SPI
Complete
Clock Sel [2:0]
Data[7:0]
Data[7:0]
TX Reg
Empty
RX Reg Full
Clock
Phase
Bypass
SS_
SS_EN_
Clock
Polarity
Int Sel
Enable
Slave
W : 00
R : 00
# : 00
RW : 00
PROGRAMMABLE TIMER REGISTERS (page 163)
0,B0h
0,B1h
0,B2h
0,B3h
0,B4h
0,B5h
0,B6h
0,B7h
0,B8h
PT0_CFG
PT0_DATA1
PT0_DATA0
PT1_CFG
PT1_DATA1
PT1_DATA0
PT2_CFG
PT2_DATA1
PT2_DATA0
DATA[7:0]
DATA[7:0]
DATA[7:0]
DATA[7:0]
DATA[7:0]
DATA[7:0]
CLKSEL One Shot START
CLKSEL One Shot START
CLKSEL One Shot START
RW : 0
RW : 00
RW : 00
RW : 0
RW : 00
RW : 00
RW : 0
RW : 00
RW : 00
USB REGISTERS (page 171)
0,58h
PMAx_DR
Data Byte[7:0]
RW : 00
106
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
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