LUPA-4000_07 Datasheet, PDF (8/38 Pages) Cypress Semiconductor – 4M Pixel CMOS Image Sensor

LUPA-4000
Sensor architecture
A schematic drawing of the architecture is given in the block
diagram below. The image core consists of a pixel array, one
X- and two Y-addressing registers (only one drawn), pixel
array drivers and column amplifiers. The image sensor of 2048
* 2048 pixels is read out in progressive scan. One or two output
amplifiers read out the image sensor. The output amplifiers are
working at 66 MHz pixel rate nominal speed or each at 33 MHz
pixel rate in case the 2 output amplifiers are used to read out
the imager. The complete image sensor has been designed for
operation up to 66 MHz.
The structure allows having a programmable addressing in the
x-direction in steps of 2 and in the y-direction in steps of 2 (only
even start addresses in X- and Y-direction are possible). The
starting point of the address is uploadable by means of the
Serial-Parallel Interface (SPI)
Figure 3. Block diagram of the image sensor
eos_y
On chip drivers
Reset, mem_hl,
precharge, sample
pixel array
2048 * 2048
Clk_y sync_y
The 6-T pixel
Clk_x
sync_x
Column amplifiers
X shift register
Logic blocks
SPI
DAC
eos_x
2 differential
outputs
To obtain the global shutter feature combined with a high
sensitivity and good Parasitic Light Sensitivity (PLS), the pixel
architecture given in the figure below is implemented.
Figure 4. 6T-pixel architecture
Vpix
Vmem
R eset
Sample
Row-Select
Document Number: 38-05712 Rev. *B
Page 8 of 38