LUPA-4000_07 Datasheet, PDF (22/38 Pages) Cypress Semiconductor – 4M Pixel CMOS Image Sensor

LUPA-4000
Standard timing (200 ns)
Figure 18. Standard timing for the R.O.T. Only pre_col and Norowsel control signals are required
In this case the control signals Norowsel and pre_col are made
active for about 20 nsec from the moment the next line is
selected. The time these pulses have to be active is related
with the biasing resistance Pre_load. The lower this
resistance, the shorter the pulse duration of Norowsel and
pre_col may be. After these pulses are given, one has to wait
for at least 180 nsec before the first pixels can be sampled. For
this mode Sh_col must be made active (low) all the time.
Back-up timing (ROT =100-200 ns)
nsec, the analog data is stored. The ROT is in this case
reduced to 100 nsec, but as the internal data was not stable
yet dynamic range is lost because not the complete analog
levels are reached yet after 100 ns.
Figure 18 shows this principle. Sh_col is now a pulse of 100
ns-200 ns starting at the same moment as pre_col and
Norowsel. The duration of Sh_col is equal to the ROT. The
shorter this time the shorter the ROT will be however this
lowers also the dynamic range.
A straightforward way of reducing the R.O.T is by using a
sample and hold function.
By means of Sh_col the analog data is tracked during the first
100 nsec during the selection of a new set of lines. After 100
In case "voltage averaging" is required, the sensor must work
in this mode with Sh_col signal and a "voltage averaging"
signal must be generated after Sh_col drops and before the
readout starts (see Figure 15)
Figure 19. Reduced standard ROT by means of Sh_col signal. pre_col (short pulse), Norowsel (short pulse) and Sh_col
(large pulse)
Precharging of the buses
This timing mode is exactly the same as the mode without
sample and hold, except that the prebus1 and prebus2 signals
are activated. It should be noticed that the precharging of the
buses can be combined with all of the timing modes discussed
above. The idea is to have a short pulse of about 5 ns to
precharge the output buses to a well-known level. This mode
makes the ghosting of bad columns impossible.
In this mode, Nsf_load must be made much larger (at least 1
Mohms).
Document Number: 38-05712 Rev. *B
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