LUPA-4000_07 Datasheet, PDF (14/38 Pages) Cypress Semiconductor – 4M Pixel CMOS Image Sensor

LUPA-4000
Table 10. Overview of bias signals (continued)
Signal
precharge_bias
Comment
Related module
Connect with 1kΩ to Vdd and capacitor of at least 200 nF to Pixel drivers
Gnd.
DC-level
1.4V
Each biasing signal determines the operation of a corre-
sponding module in the sense that it controls speed and dissi-
pation. Some modules have 2 biasing resistors: one to achieve
the high speed and another to minimize power dissipation.
Pixel array signals
The Pixel array of the image sensor requires digital control
signals and several different power supplies. This paragraph
explains the relation between the control signals and the
applied supplies and the internal generated pixel array signals.
From Figure 9 one can see that the internal generated pixel
array signals are Reset, Sample, Precharge, Vmem and
Row_select. These are internal generated signals derived by
on chip drivers from external applied signals. Row_select is
generated by the y addressing and will not be discussed in this
paragraph.
The function of each of the signals is:
Reset: Resets the pixel and initiates the integration time. If
reset is high than the photodiode is forced to a certain voltage,
depending on Vpix, which is the pixel supply; and depending
on the high level of reset signal. The higher these signals or
supplies are, the higher the voltage-swing. The limitation on
the high level of Reset and Vpix is 3.3V. Nevertheless, it has
no sense increasing Vpix without increasing the reset level.
The opposite does make sense. Additionally, it is this reset
pulse that also controls the dual or multiple slope feature
inside the pixel. By giving a reset pulse during integration, but
not at full reset level, the photodiode is reset to a new value,
only if his value is sufficient decreased due to light illumination.
The low level of reset is 0V, but the high level is 2.5V or higher
(3.3V) for the normal reset and a lower (<2.5V) level for the
multiple slope reset.
Precharge: Precharge serves as a load for the first source
follower in the pixel and is activated to overwrite the current
information on the storage node by the new information on the
photodiode. Precharge is controlled by an external digital
signal between 0 and 2.5V.
Sample: Samples the photodiode information onto the
memory element. This signal is also a standard digital level
between 0 and 2.5V.
Vmem: this signal increases the information on the memory
element with a certain offset. This way one can increase the
output voltage variation. Vmem changes between Vmem_l
(2.5V) and Vmem_h (3.3V).
Figure 10. Internal timing of the pixel. Levels are defined by the pixel array voltage supplies (For the correct polarities
of the signals refer to Table 11)
The signals in Figure 10 are generated from the on chip
drivers. These on chip drivers need 2 types of signals to
generate the exact type of signal. It needs digital control
signals between 0 and 3.3V (internally converted to 2.5V) with
normal driving capability and power supplies. The control
signals are required to indicate the moment they need to occur
and the power supplies indicate the level.
Vmem is made of a control signal Mem_hl and 2 supplies
Vmem_h and Vmem_l. If the signal Mem_hl is the logic "0"
than the internal signal Vmem is low, if Mem_hl is logic "1" the
internal signal Vmem is high.
Reset is made by means of 2 control signals: Reset and
Reset_ds and 2 supplies: Vres and Vres_ds. Depending on
the signal that becomes active, the corresponding supply level
is applied to the pixel.
Table 11 summarizes the relation between the internal and
external pixel array signals.
Document Number: 38-05712 Rev. *B
Page 14 of 38