LUPA-4000_07 Datasheet, PDF (15/38 Pages) Cypress Semiconductor – 4M Pixel CMOS Image Sensor

LUPA-4000
Table 11. Overview of the in- and external pixel array signals
Internal Signal
Vlow
Precharge
0
Sample
0
Reset
0
Vmem
2.0- 2.5V
Vhigh
0.45V
2.5V
2.5 - 3.3V
2.5-3.3V
External control signal
Precharge (AL)
Sample (AL)
Reset (AH) & Reset_ds
(AH)
Mem_hl (AL)
Low DC-level
Vpre_l
Gnd
Gnd
Vmem_l
High DC-level
Controlled by bias-resistor
Vdd
Vres & Vres_ds
Vmem_h
In case the dual slope operation is desired, one needs to give
a second reset pulse to a lower reset level during integration.
This can be done by the control signal Reset_ds and by the
power supply Vres_ds that defines the level to which the pixel
has to be reset.
Note that Reset is dominant over Reset_ds, which means that
the high voltage level will be applied for reset, if both pulses
occur at the same time.
Note that multiple slopes are possible having multiple
Reset_ds pulses with a lower Vres_ds level for each pulse
given within the same integration time
The rise and fall times of the internal generated signals are not
very fast (200 nsec). In fact they are made rather slow to limit
the maximum current through the power supply lines
(Vmem_h, Vmem_l, Vres, Vres_ds, Vdd). Current limitation of
those power supplies is not required. Nevertheless, it is
advisable to limit the currents not higher than 400 mA.
The power supply Vmem_l must be able to sink this current
because it must be able to discharge the internal capacitance
from the level Vmem_h to the level Vmem_l. The external
control signals should be capable of driving input capacitance
of about 10 pF.
Digital signals
The digital signals control the readout of the image sensor.
These signals are:
• Sync_y (AH): Starts the readout of the frame. This pulse
synchronises the y-address register: active high. This signal
is at the same time the end of the frame or window and
determines the window width.
• Clock_y (AH): Clock of the y-register. On the rising edge of
this clock, the next line is selected.
• Sync_x (AH): Starts the readout of the selected line at the
address defined by the x-address register. This pulse
synchronises the x-address register: active high. This signal
is at the same time the end of the line and determines the
window length.
• Clock_x (AH): Determines the pixel rate. A clock of 33 MHz
is required to achieve a pixel rate of 66MHz.
• Spi_data (AH): the data for the SPI
• Spi_clock (AH): clock of the serial parallel interface. This
clock downloads the data into the SPI register.
• Spi_load (AH): when the SPI register is uploaded, then the
data will be internally available on the rising edge of
SPI_load.
• Sh_kol (AL): control signal of the column readout. Is used
in sample & hold mode and in binning mode.
• Norowsel (AH): Control signal of the column readout. (See
timing).
• Pre_col (AL): Control signal of the column readout to reduce
row blanking time.
• Voltage averaging (AH): Signal required obtaining voltage
averaging of 2 pixels.
Test signals
The test structures implemented in this image sensor are:
• Array of pixels (6*12) which outputs are tied together: used
for spectral response measurement.
• Temperature diode (2): Apply a forward current of 10-100
µA and measure the voltage V_T of the diode. V_T varies linear
with the temperature (V_T decreases with approximately 1,6
mV/°C).
• End of scan pulses (do not use to trigger other signals):
• Eos_x: end of scan signal: is an output signal, indicating
when the end of the line is reached. Is not generated when
doing windowing.
• Eos_y: end of scan signal: is an output signal, indicating
when the end of the frame is reached. Is not generated
when doing windowing.
• Eos_spi: output signal of the SPI to check if the data is
transferred correctly through the SPI.
Notes
5. AH: Active High
6. AL: Active Low
Document Number: 38-05712 Rev. *B
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