LUPA-4000_07 Datasheet, PDF (13/38 Pages) Cypress Semiconductor – 4M Pixel CMOS Image Sensor

LUPA-4000
Table 9. Overview of the power supplies related to the pixel signals
Name
DC current Max. current Min.
Typ.
Max.
Vres
1 mA
200 mA
2.5V
3.5V
3.8V
Vres_ds
1 mA
200 mA
2.0V
2.5V
3.3V
Vmem_h 1 mA
200 mA
2.5V
3.3V
3.5V
Vmem_l
1 mA
200 mA
2.0V
2.5 V
3.0V
Vdd
1 mA
200 mA
2.0V
2.5V
3.0V
Vpix
12 mA
500 mA
2.0V
2.5V
3.3V
Vpre_l
1 mA
200 mA
–400 mV 0V
0V
Description
Power supply reset drivers.
Power supply dual slope reset drivers.
Power supply memory elements in pixel for
high voltage level
Power supply memory elements in pixel for
low voltage level. Should be tuneable
Power supply for Sample
Power supply pixel array. Should be
tuneable to 3.3V
Power supply for Precharge in off-stat. May
be connected to ground.
The maximum currents mentioned in Table 8 and Table 9 are
peak currents which occur once per frame (except for Vres_ds
in multiple slope mode). All power supplies should be able to
deliver these currents except for Vmem_l and Vpre_l, which
must be able to sink this current.
The maximum peak current for Vpix should not be higher than
500 mA. It is important to notice that no power supply filtering
on chip is implemented and that noise on these power supplies
can contribute immediately to the noise on the signal.
Especially the voltage supplies Vpix and Vaa are important to
be well noise free.
Start-up sequence
The LUPA-4000 will go in latch up (draw high current) as soon
as all power supplies are turned on at the same time. The
sensor will come out of latch-up and start working normally as
soon as it is being clocked. A power supply with a 400 mA limit
is recommended to avoid damage to the sensor. It is
recommended to avoid the time that the device is in the
latch-up state, so clocking of the sensor should start as soon
as possible (i.e. as soon as the system is turned on).
In order to completely avoid latch-up of the image sensor, the
next sequence should be taken into account:
• Apply Vdd
• Apply clocks and digital pulses to the sensor to count 2048
clocks and 2048 clock_y pulses to empty the shift registers
• Apply other supplies
Biasing and analog signals
The analog output levels that may be expected are between
0.3V for a white, saturated, pixel and 1.3V for a black pixel.
2 Output stages are foreseen, each consisting of 2 output
amplifiers, resulting in 4 outputs. 1 Output amplifier is used for
the analog signal resulting from the pixels. The second
amplifier is used for a dc reference signal. The dc-level from
the buffer is defined by a DAC, which is controlled by a 7-bit
word downloaded in the SPI. Additionally, an extra bit in the
SPI defines if 1 output or the 2 output stages are used.
Table 10 summarizes the biasing signals required to drive this
image sensor. For optimisation reasons of the biasing of the
column amplifiers with respect to power dissipation, we need
several biasing resistors. This optimisation results in an
increase of signal swing and dynamic range.
Table 10. Overview of bias signals
Signal
Out_load
dec_x_load
muxbus_load
nsf_load
uni_load_fast
uni_load
pre_load
col_load
dec_y_load
psf_load
Comment
Connect with 60 KΩ to Voo and capacitor of 100 nF to Gnd
Connect with 2 MΩ to Vdd and capacitor of 100 nF to Gnd
Connect with 25 KΩ to Vaa and capacitor of 100 nF to Gnd
Connect with 5 KΩ to Vaa and capacitor of 100 nF to Gnd
Connect with 10 KΩ to Vaa and capacitor of 100 nF to Gnd
Connect with 1 MΩ to Vaa and capacitor of 100 nF to Gnd
Connect with 3 KΩ to Vaa and capacitor of 100 nF to Gnd
Connect with 1 MΩ to Vaa and capacitor of 100 nF to Gnd
Connect with 2 MΩ to Vdd and capacitor of 100 nF to Gnd
Connect with 1 MΩ to Vaa and capacitor of 100 nF to Gnd
Related module
Output stage
X-addressing
Multiplex bus
Column amplifiers
Column amplifiers
Column amplifiers
Column amplifiers
Column amplifiers
Y-addressing
Column amplifiers
DC-level
0.7 V
0.4 V
0.8 V
1.2 V
1.2 V
0.5 V
1.4 V
0.5 V
0.4 V
0.5 V
Document Number: 38-05712 Rev. *B
Page 13 of 38