BCM43362SKUBGT Datasheet, PDF (77/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ b/g/n MAC/Baseband/Radio + SDIO

BCM43362 Data Sheet
SDIO Default Mode Timing
Table 24: SDIO Bus Timing ^a Parameters (Default Mode)
Parameter
Frequency—Data Transfer mode
Frequency—Identification mode
Clock low time
Clock high time
Clock rise time
Clock fall time
Symbol
fPP
fOD
tWL
tWH
tTLH
tTHL
Inputs: CMD, DAT (referenced to CLK)
Input setup time
tISU
Input hold time
tIH
Outputs: CMD, DAT (referenced to CLK)
Output delay time—Data Transfer mode
Output delay time—Identification mode
tODLY
tODLY
a. Timing is based on CL  40 pF load on CMD and Data.
b. min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.
Minimum
0
0
10
10
–
–
Typical
–
–
–
–
–
–
5
–
5
–
0
–
0
–
Maximum Unit
25
MHz
400
kHz
–
ns
–
ns
10
ns
10
ns
–
ns
–
ns
14
ns
50
ns
Broadcom_®
February 13, 2015 • 43362-DS106-R
IEEE 802.11 b/g/n MAC/Baseband/Radio + SDIO
Page 76
BROADCOM CONFIDENTIAL