BCM43362SKUBGT Datasheet, PDF (23/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ b/g/n MAC/Baseband/Radio + SDIO

BCM43362 Data Sheet
WLAN System Interfaces
Section 4: WLAN System Interfaces
SDIO v2.0
The BCM43362 WLAN section supports SDIO version 2.0. for both 1-bit (25 Mbps), 4-bit modes (100 Mbps),
and high speed 4-bit (50 MHz clocks—200 Mbps). It has the ability to map the interrupt signal on a GPIO pin.
This out-of-band interrupt signal notifies the host when the WLAN device wants to turn on the SDIO interface.
The ability to force control of the gated clocks from within the WLAN chip is also provided.
SDIO mode is enabled using the strapping option pins. See Table 10 on page 56 for details.
Three functions are supported:
• Function 0 Standard SDIO function (Max BlockSize/ByteCount = 32B)
• Function 1 Backplane Function to access the internal System On Chip (SOC) address space (Max
BlockSize/ByteCount = 64B)
• Function 2 WLAN Function for efficient WLAN packet transfer through DMA (Max BlockSize/ByteCount =
512B)
SDIO Pin Descriptions
Table 4: SDIO Pin Descriptions
DATA0
DATA1
DATA2
DATA3
CLK
CMD
SD 4-Bit Mode
Data line 0
DATA
Data line 1 or Interrupt IRQ
Data line 2
NC
Data line 3
NC
Clock
CLK
Command line
CMD
SD 1-Bit Mode
Data line
Interrupt
Not used
Not used
Clock
Command line
DO
IRQ
NC
CS
SCLK
DI
gSPI Mode
Data output
Interrupt
Not used
Card select
Clock
Data input
Figure 7: Signal Connections to SDIO Host (SD 4-Bit Mode)
CLK
SD Host
CMD
DAT[3:0]
BCM43362
Broadcom_®
February 13, 2015 • 43362-DS106-R
IEEE 802.11 b/g/n MAC/Baseband/Radio + SDIO
Page 22
BROADCOM CONFIDENTIAL