BCM43362SKUBGT Datasheet, PDF (45/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ b/g/n MAC/Baseband/Radio + SDIO

BCM43362 Data Sheet
GPIO Interface
GPIO Interface
Five general purpose I/O (GPIO) pins are available on the BCM43362 that can be used to connect to various
external devices.
GPIOs are tristated by default. Subsequently, they can be programmed to be either input or output pins via the
GPIO control register. They can also be programmed to have internal pull-up or pull-down resistors.
GPIO_0 is initially used as a strapping option to select between SDIO and SPI modes.
GPIOs 3, 4, and 5 are multiplexed with the Bluetooth Coexistence Interface. By default, these pins are
BT_COEX pins. Software can reprogram these pins to behave as GPIOs.
GPIO_1 is a GPIO by default, but can be reprogrammed by software to become the BTCX_FREQ signal.
JTAG Interface
The BCM43362 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and
PCB assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist
customers by using proprietary debug and characterization test tools during board bring-up. Therefore, it is
highly recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs.
UART Interface
One UART interface can be enabled by software as an alternate function on the JTAG pins. UART_RX is
available on the JTAG_TDI pin, and UART_TX is available on the JTAG_TDO pin.
The UART is primarily for debugging during development. By adding an external RS-232 transceiver, this UART
enables the BCM43362 to operate as RS-232 data termination equipment (DTE) for exchanging and managing
data with other serial devices. It is compatible with the industry standard 16550 UART, and it provides a FIFO
size of 64 × 8 in each direction.
Broadcom_®
February 13, 2015 • 43362-DS106-R
IEEE 802.11 b/g/n MAC/Baseband/Radio + SDIO
Page 44
BROADCOM CONFIDENTIAL