BCM43362SKUBGT Datasheet, PDF (51/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ b/g/n MAC/Baseband/Radio + SDIO

BCM43362 Data Sheet
Signal Assignments
Ball #
G7
Clocks
A7
D6
D7
F6
J5
Table 8: WLBGA Signal Descriptions (Cont.)
Signal Name
Type Description
JTAG_TRST_L
I
For normal operation, connect as described in the JTAG
specification (IEEE Std 1149.1). Otherwise, if JTAG is not used,
this pin can be left unconnected (NC) as it has an internal weak
pull-up resistor.
JTAG drive strength:
For 1.8V: 1.0 mA
For 2.5V: 2.5 mA
For 3.3V: 3.0 mA
Output slewing can be enabled or disabled by software; it is enabled by default.
WRF_TCXO_IN
I
Reference clock input for use when sharing a TCXO with
another chip, such as a BT/FM/GPS chip (see “Frequency
References” on page 18). This input has an internal DC
blocking capacitor, so do not include an external DC blocking
capacitor. Connect directly to the external TCXO. This input pad
is powered by the WRF_TCXO_VDD3P3 supply, which should
be continually powered whenever the external TCXO is
powered, even when the BCM43362 is in reset, thereby
ensuring this input maintains a constant load on the TCXO
signal in all device modes. If unused, ground this pin.
OSCOUT
O XTAL oscillator amplifier output. See “Frequency References”
on page 18.
OSCIN
I
XTAL oscillator amplifier input. This pin can also be used as the
reference clock input from a dedicated (that is, not shared)
TCXO.
XTAL_PU
O External reference clock enable (Clock_Request)
Default mode (open source): XTAL_PU is driven HIGH when the clock is requested and pulled
low with a weak internal pull-down resistor when the clock is not requested.
Push-Pull: Always driven HIGH or LOW (no PU/PD). Push-Pull mode is enabled by software.
XTAL_PU internal pull-down (PD) resistances:
PD @ 1.8V (minimum, typical, maximum): 356 kΩ, 558 kΩ, 651 kΩ
PD @ 2.5V (minimum, typical, maximum): 356 kΩ, 559 kΩ, 652 kΩ
PD @ 3.3V (minimum, typical, maximum): 356 kΩ, 559 kΩ, 653 kΩ
XTAL_PU drive strength:
For 1.8V: 2.0 mA
For 2.5V: 5.0 mA
For 3.3V: 6.0 mA
Output slewing can be enabled or disabled by software; it is enabled by default.
EXT_SLEEP_CLK
I
Input pin for optional high-precision 32.768 kHz Clock (Sleep
Clock).
Broadcom_®
February 13, 2015 • 43362-DS106-R
IEEE 802.11 b/g/n MAC/Baseband/Radio + SDIO
Page 50
BROADCOM CONFIDENTIAL