BCM43362SKUBGT Datasheet, PDF (31/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ b/g/n MAC/Baseband/Radio + SDIO

BCM43362 Data Sheet
Generic SPI Mode
gSPI Host-Device Handshake
To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN/Chip by writing
to the wake-up WLAN register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the
BCM43362 is ready for data transfer. The device can signal an interrupt to the host indicating that the device is
awake and ready. This procedure also needs to be followed for waking up the device in sleep mode. The device
can interrupt the host using the WLAN IRQ line whenever it has any information to pass to the host. On getting
an interrupt, the host needs to read the interrupt and/or status register to determine the cause of interrupt and
then take necessary actions.
Boot-Up Sequence
After power-up, the gSPI host needs to wait 50 ms for the device to be out of reset. For this, the host needs to
poll with a read command to F0 addr 0x14. Address 0x14 contains a predefined bit pattern. As soon as the host
gets a response back with the correct register content, it implies that the device has powered up and is out of
reset. After that, the host needs to set the wakeup-WLAN bit (F0 reg 0x00 bit 7). Wakeup-WLAN turns the PLL
on; however, the PLL doesn't lock until the host programs the PLL registers to set the crystal frequency.
For the first time after power-up, the host needs to wait for the availability of low-power clock inside the device.
Once that is available, the host needs to write to a PMU register to set the crystal frequency. This will turn on
the PLL. After the PLL is locked, the chipActive interrupt is issued to the host. This indicates device awake/ready
status. See Table 6 for information on gSPI registers.
In Table 6, the following notation is used for register access:
• R: Readable from host and CPU
• W: Writable from host
• U: Writable from CPU
Address Register
Bit
x0000 Word length
0
Endianess
1
High-speed mode 4
Interrupt polarity 5
Wake-up
7
Table 6: gSPI Registers
Access Default
R/W/U 0
R/W/U 0
R/W/U 1
R/W/U 1
R/W 0
Description
0: 16-bit word length
1: 32-bit word length
0: Little Endian
1: Big Endian
0: Normal mode. Sample on SPICLK rising edge,
output on falling edge.
1: High-speed mode. Sample and output on rising
edge of SPICLK (default).
0: Interrupt active polarity is low.
1: Interrupt active polarity is high (default).
A write of 1 will denote wake-up command from
host to device. This will be followed by a F2
Interrupt from gSPI device to host, indicating
device awake status.
Broadcom_®
February 13, 2015 • 43362-DS106-R
IEEE 802.11 b/g/n MAC/Baseband/Radio + SDIO
Page 30
BROADCOM CONFIDENTIAL