BCM43362SKUBGT Datasheet, PDF (76/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ b/g/n MAC/Baseband/Radio + SDIO

BCM43362 Data Sheet
Interface Timing and AC Characteristics
Section 14: Interface Timing and AC
Characteristics
Note: Values in this document are design goals and are subject to change based on the results of
device characterization.
Unless otherwise stated, the specifications in this section apply when the operating conditions are within the
limits specified in Table 12 on page 58 and Table 14 on page 59. Functional operation outside of these limits is
not guaranteed.
SDIO Default Mode Timing
SDIO default mode timing is shown by the combination of Figure 25 and Table 24 on page 75.
Figure 25: SDIO Bus Timing (Default Mode)
f_PP
t_WL
t_WH
SDIO_CLK
Input
t_THL
t_ISU
t_TLH
t_IH
Output
t_ODLY
(max)
t_ODLY
(min)
Table 24: SDIO Bus Timing ^a Parameters (Default Mode)
Parameter
Symbol Minimum Typical
SDIO CLK (All values are referred to minimum VIH and maximum VIL^b)
Maximum Unit
Broadcom_®
February 13, 2015 • 43362-DS106-R
IEEE 802.11 b/g/n MAC/Baseband/Radio + SDIO
Page 75
BROADCOM CONFIDENTIAL