BCM43362SKUBGT Datasheet, PDF (32/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ b/g/n MAC/Baseband/Radio + SDIO

BCM43362 Data Sheet
Generic SPI Mode
Table 6: gSPI Registers (Cont.)
Address Register
Bit
x0002 Status enable
0
x0003
x0004
Interrupt with
1
status
Reserved
–
Interrupt register 0
1
2
5
6
7
x0005 Interrupt register 5
6
7
x0006, Interrupt enable 15:0
x0007 register
x0008 to Status register 31:0
x000B
x000C, F1 info register 0
x000D
1
13:2
x000E, F2 info register 0
x000F
1
15:2
x0014 to Test–Read only 31:0
x0017 register
x0018 to Test–R/W register 31:0
x001B
x001C to Response delay 7:0
x001F registers
Access Default
R/W 1
R/W 0
–
–
R/W 0
R
R
R
R
R
R
R
R
R/W/U
0
0
0
0
0
0
0
0
16'hE0E7
R
32'h0000
Description
0: no status sent to host after read/write
1: status sent to host after read/write
0: do not interrupt if status is sent
1: interrupt host even if status is sent
–
Requested data not available; Cleared by writing
a 1 to this location
F2/F3 FIFO underflow due to last read
F2/F3 FIFO overflow due to last write
F2 packet available
F3 packet available
F1 overflow due to last write
F1 Interrupt
F2 Interrupt
F3 Interrupt
Particular Interrupt is enabled if a corresponding
bit is set
Same as status bit definitions
R
R
R/U
R/U
R
R/U
R
R/W/U
R/W
1
F1 enabled
0
F1 ready for data transfer
12'h40
F1 max packet size
1
F2 enabled
0
F2 ready for data transfer
14'h800 F2 max packet size
32'hFEEDB This register contains a predefined pattern, which
EAD
the host can read and determine if the gSPI
interface is working properly.
32'h000000 This is a dummy register where the host can write
00
some pattern and read it back to determine if the
gSPI interface is working properly.
0x1D = 4,
other
registers =
0
Individual response delays for F0, F1, F2, and F3.
The value of the registers is the number of byte
delays that are introduced before data is shifted
out of the gSPI interface during host reads.
Figure 15 on page 32 shows the WLAN boot-up sequence from power-up to firmware download, including the
initial device power-on reset (POR) evoked by the WL_RST_N signal. After initial power-up, the WL_RST_N
signal can be held low to disable the BCM43362 or pulsed low to induce a subsequent reset.
Note: The BCM43362 has an internal power-on reset (POR) circuit. The device will be held in reset for
a maximum of 3 ms after VDD and VDDIO have both passed the 0.6V threshold.
Broadcom_®
February 13, 2015 • 43362-DS106-R
IEEE 802.11 b/g/n MAC/Baseband/Radio + SDIO
Page 31
BROADCOM CONFIDENTIAL