IBIS4-14000-M Datasheet, PDF (21/30 Pages) Cypress Semiconductor – 14-Megapixel CMOS Image Sensor

IBIS4-14000-M
IBIS4-14000-C
Table 13. Pin List(continued)
Pin #
Name
30
VDDR
Function
Power supply for reset line drivers.
31
VDD
Power supply.
32
GND
Ground.
33
GNDAB
Anti-blooming reference level (= pin 33).
34
SELECT Control select line of pixel array.
35
RESET
Reset of the selected row of pixels.
36
CBIAS
Bias current column amplifiers.
37
PCBIAS
Bias current.
38
DIN
Serial data input.
39
SCLK
SPI interface clock.
40
CS
Chip select.
41
PC
Row initialization pulse.
42
SYNC_X Sets the X shift register to row 1.
43
GND
44
VDD
45
CLK_X
46
SHR
47
SHS
48
XBIAS
Ground.
Power supply.
Clock of YR shift register.
Row track & hold reset level
(1 = hold; 0 = track).
Row track & hold signal level (1 = hold;
0 = track).
Bias current X multiplexer.
49
ABIAS
Bias current pixel array.
Comment
Nominal 4V.
Connected on-chip to pin 21.
Nominal 3.3V
0V
Typ. 0V. Set to 1V for improved anti-blooming.
High active. See timing diagrams.
High active. See timing diagrams.
Connect with 22 kΩ to VDD and decouple with 100 nF to
GND.
Connect with 22 kΩ to VDD and decouple with 100 nF to
GND.
16-bit word. LSB first.
Shifts on rising edge.
Data copied to registers on rising edge.
See timing diagrams.
Low active. Synchronous sync on rising edge of CLK_X
150 ns set-up time.
0V
Nominal 3.3V
Shifts on rising edge.
See timing diagram.
See timing diagram.
Connect with 10 kΩ to VDD and decouple with 100 nF to
GND.
Connect with 10 MΩ to VDD and decouple with 100 nF to
GND.
Document #: 38-05709 Rev. *A
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