IBIS4-14000-M Datasheet, PDF (14/30 Pages) Cypress Semiconductor – 14-Megapixel CMOS Image Sensor

IBIS4-14000-M
IBIS4-14000-C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
mode F - 1:12
Figure 11. F Subsample Mode
2.4 Sensor Readout Timing Diagrams
2.4.1 Row Sequencer
The row sequencer controls pulses to be given at the start of
each new line. Figure 12 shows the timing diagram for this
sequence.
The signals to be controlled at each row are:
• CLK_YL and CLK_YR: These are the clocks of the YL and
YR shift register. They can be driven by the same signals
and at a continuous frequency. At every rising edge, a new
row is being selected.
• SELECT: This signal connects the pixels of the currently
sampled line with the columns. It is important that PC and
SELECT are never active together.
• PC: An initialization pulse that needs to be given to
precharge the column.
• SHS (Sample & Hold pixel Signal): This signal controls the
track & hold circuits in the column amplifiers. It is used to
sample the pixel signal in the columns. (0 = track ; 1 = hold)
• RESET: This pulse resets the pixels of the row that is
currently being selected. In rolling shutter mode, the RESET
signal is pulsed a second time to reset the row selected by
the YR shift register. For “reset black” dark reference
signals, the reset pulse can be pulsed also during the first
PC pulse. Normally, the rising edge of RESET and the falling
edge of PC occur at the same position. The falling edge of
RESET lags behind the rising PC edge.
• SHR (Sample & Hold pixel Reset level): this signal controls
another track & hold circuit in the column amplifiers. It is
used to sample the pixel reset level in the columns (for
double sampling). (0 = track ; 1 = hold)
• SYL (Select YL register): Selects the YL shift register to
drive the reset line of the pixel array
• SYR (Select YR register): Selects the YR shift register to
drive the reset line of the pixel array. For rolling shutter appli-
cations, SYL and SYR are complementary. In full frame
readout, both registers may be selected together, only if it
is guaranteed that both shift registers point to the same row.
This can reduce the row blanking time.
• SYNC_YR and SYNC_YL: Synchronization pulse for the
YR and YL shift registers. The SYNC_YR/SYNC_YL signal
is clocked in during a rising edge on CLK_YR/CLK_YL and
resets the YR/YL shift register to the first row. Both pulses
are pulsed only once each frame. The exact pulsing scheme
depends on the mode of use (full frame/ rolling shutter). A
200 ns set-up time applies. See Table 9.
• SYNC_X: Resets the column pointer to the first row. This
has to be done before the end of the first PC pulse, in case
when the previous line has not been read out completely.
Figure 12 shows the basic timing diagram of the IBIS4-14000
image sensor and Table 9 shows the timing specifications of
the clocking scheme
Document #: 38-05709 Rev. *A
Page 14 of 30