IBIS4-14000-M Datasheet, PDF (15/30 Pages) Cypress Semiconductor – 14-Megapixel CMOS Image Sensor

IBIS4-14000-M
IBIS4-14000-C
CLOCK_YL
k
SYNC_YR
a
SYNC_YL
PC
l
b
b
SHS
SELECT
RESET
SHR
SYL
SYR
c
f
d
e
h
Optional reset pulse
for reset black
g
h
m
d
e
c
f
i
j
j
h
Once each
frame
For each
new row
Figure 12. Line Readout Timing
Table 9. Timing Constraints for the Row Sequencer
Only when the electronic
shutter is used
Symbol
a
b
c
d
e
f
g
h
i
j
k
l
m
Min.
200 ns
h+2*CLK
Typ.
600 ns
2.7 µs
10 µs
1.3 µs
6.5 µs
100 ns
1.4 µs
5 µs
1.28 µs
500 ns
240 ns
3µs
500ns
Description
Min. SYNC set-up times. SYNC_Y is clocked in on rising edge on CLK_Y. SYNC_Y pulse
must overlap CLK_Y by one clock period. Set-up times of 200 ns apply after SYNC edges.
Within this set-up time no rising CLK edge may occur
Duration of PC pulse
Delay between falling edge on PC and rising edge on SHS/SHR. Duration of SHS/SHR
pulse
Delay between rising edge on PC and rising edge on SELECT
Delay between rising edge on SELECT and rising edge on SHS/SHR.
Delay between rising edge on SHS and falling edge on SELECT.
Delay between falling edge of SELECT and rising edge of RESET
Duration of RESET pulse
Delay between rising edge on SHR and rising edge on SYR
SYL and SYR pulses must overlap second RESET pulse at both sides by one clock cycle
Duration of CLOCK_Y pulse
Delay between falling edge of CLK_Y and Falling edge of PC and SHS
Delay between falling edge of RESET and falling edge of PC and SHR
Notes:
CLK = one clock period of the master clock, shortest system
time period available.
In the above timing diagram, the YR shift register is used for
the electronic shutter. The CLK_YR is driven identically as
CLK_YL. The SYNC_YR pulse leads the SYNC_YL pulse by
a given number of rows. Relative to the row timing, both SYNC
pulses are given at the same time position.
SYNC_YR and SYNC_YL are only pulsed once each frame,
SYNC_YL is pulsed when the first row will be read out and
Document #: 38-05709 Rev. *A
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