IBIS4-14000-M Datasheet, PDF (19/30 Pages) Cypress Semiconductor – 14-Megapixel CMOS Image Sensor

IBIS4-14000-M
IBIS4-14000-C
Table 12. Serial Sensor Parameters Register Bit Definitions
BIT
0 (LSB)
1
2
3
4
5
6
7
8
9
10
11
12
Description’
set to zero (0)
1 = power on sensor array ; 0 = power-down
1 = power up output amplifier 4; 0 = power-down
1 = power up output amplifier 3; 0 = power-down
1 = power up output amplifier 2; 0 = power-down
1 = power up output amplifier 1; 0 = power-down
3-bit code for subsampling mode of X shift register:
000 = full resolution
011 = select 4, skip 20
001 = full resolution
100 = select 4, skip 4
010 = full resolution
101 = select 4, skip 8
3-bit code for subsampling mode of Y shift registers:
000 = select 2, skip 2
011 = select 2, skip 4
001 = full resolution
100 = select 2, skip 2
010 = select 2, skip 2
101 = select 2, skip 2
Crossbar switch (output multiplexer) control bit initial value.
This initial value is clocked into the crossbar switch at a SYNC_YR rising edge pulse (when the array
pointers jump back to row 1).
The crossbar switch control bit selects the correspondence between multiplexer busses and output ampli-
fiers. Bus-to-output correspondence is according to the following table:
13
14
15 (MSB)
Bus
when bit set to 0
1
output 1
2
output 2
3 (4 outputs) output 3
4 (4 outputs) output 4
when bit set to 1
output 2
output 1
output 4
output 3
1 = Toggle crossbar switch control bit on every odd/even line. In order to let green pixels always use the
same output amplifier automatically, this bit must be set to 1. On every CLK_Y rising edge (when a new
row is selected), the crossbar switch control bit will toggle. Initial value (after SYNC_Y) is set by bit 12.
Not used.
1 = Power-up sensor array; 0 = Power-down
3 pins are used for the serial data interface. This interface
converts the serial data into an (internal) parallel data bus
(Serial-Parallel Interface or SPI). The control lines are:
• DATA: the data input. LSB is clocked in first.
• CLK: clock, on each rising edge, the value of DATA is
clocked in
• CS: chip select, a rising edge on CS loads the parallelized
data into the on-chip register.
The initial state of the register is undefined. However, no state
exists that destroys the device.
Document #: 38-05709 Rev. *A
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