IBIS4-14000-M Datasheet, PDF (18/30 Pages) Cypress Semiconductor – 14-Megapixel CMOS Image Sensor

IBIS4-14000-M
IBIS4-14000-C
2.5 SPI Register
2.5.1 SPI Interface Architecture
The elementary unit cell of the serial to parallel interface
consists of two D-flip-flops. The architecture is shown in
To sensor core
Figure 15. 16 of these cells are connected in parallel, having
a common /CS and SCLK form the entire uploadable
parameter block, where D_in is connected to D_out of the next
cell. The uploaded settings are applied to the sensor on the
rising edge of signal /CS.
16 outputs to sensor core
D
Q
CS
C
Din
SCLK
D
Q
C
Unity Cell
Din
SCLK
Dout
Entire uploadable parameter block
CS
Dout
SCLK
Din
CS
Data
valid
Tsclk
D0
D1
D2
Th
D15
Ts
Figure 15. SPI Interface
Table 11. Timing Requirements Serial-Parallel Interface
Parameter
Tsclk
Ts
Th
Value
100 ns
50 ns
50 ns
2.5.2 SPI Register Definition
Sensor parameters can be serially uploaded inside the sensor
at the start of a frame. The parameters are:
• Subsampling modes for X and Y shift registers (3-bit code
for 6 subsampling modes)
• Power control of the output amplifiers, column amps and
pixel array. Each amplifier can be individually powered
up/down
• Output crossbar switch control bits. The crossbar switch is
used to route the green pixels to the same output amplifiers
at all time. A first bit controls the crossbar. When a second
bit is set, the first bit will toggle on every CLK_Y edge in
order to automatically route the green pixels of the bayer
filter pattern.
The code is uploaded serially as a 16-bit word (LSB uploaded
first).
Table 12 lists the register definition. The default code for a full
resolution readout is 33342 (decimal) or 1000 0010 0011 1110.
Document #: 38-05709 Rev. *A
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