IBIS4-14000-M Datasheet, PDF (20/30 Pages) Cypress Semiconductor – 14-Megapixel CMOS Image Sensor

IBIS4-14000-M
IBIS4-14000-C
3.0 Pin Configuration
Table 12 lists the pin configuration of the IBIS4-14000.
Figure 17 shows the assignment of pin numbers on the
package.
Table 13. Pin List
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Name
Function
Comment
OBIAS
Bias current output amplifiers.
Connect with 10kΩ to VDD and decouple with 100 nF to
GND.
GND
Ground for output 3.
OUT3
Output 3.
GND
Ground for output 4.
OUT4
Output 4.
VDD
Power supply.
Nominal 3.3V
GND
Ground.
0V
OUT2
Output 2.
GND
Ground for output 2.
OUT1
Output 1.
GND
Ground for output 1.
DARKREF Offset level of output signal.
Typ. 2.6V. min. 1.7V max. 3V
TEMP1
Temperature sensor.
Located near the output amplifiers (pixel
4536, 0) near the stitch line).
Any voltage above GND forward biases the diode.
Connect to GND if not used.
PHDIODE
Photodiode output.
Yields the equivalent photocurrent of 250 x
50 pixels. Diode is located right under the
pad.
Reverse biased by any voltage above GND
Connect to GND if not used.
CLK_Y
Y clock for switchboard.
Clocks on rising edge
Connect to CLK_YL (or drive identically)
SYNC_Y Y SYNC pulse for switchboard.
Low active: synchronous sync on rising edge of CLK_Y
Connect to SYNC_YL (or drive identically)
TEMP2
Temperature sensor.
Located near pixel (24,0).
Any voltage above GND forward biases the diode.
Connect to GND if not used.
GNDAB
Anti-blooming reference level (= pin 33). Typ. 0V. Set to 1.5V for improved anti-blooming.
GND
Ground.
0V
VDD
Power supply.
Nominal 3.3V
VDDR
Power supply for reset line drivers
Nominal 4V
Connected on-chip to pin 30
CLK_YR Clock of YR shift register.
Shifts on rising edge.
SYR
Activate YR shift register for driving of reset High active. Exact pulsing pattern see timing diagram.
and select line of pixel array.
Both SYR = 1 and SYL = 1 is not allowed, except when the
same row is selected!
SYNC_YR Sets the YR shift register to row 1.
Low active. Synchronous sync on rising edge of CLK_YR
200 ns set-up time
VDDARRAY Pixel array power supply (= pin 26).
3V
VDDARRAY Pixel array power supply (= pin 25).
3V
SYNC_YL Sets the YL shift register to row 1.
Low active. Synchronous sync on rising edge of CLK_YL
200 ns set-up time.
SYL
Activate YL shift register for driving of reset High active. Exact pulsing pattern see timing diagram.
and select line of pixel array.
Both SYR = 1 and SYL = 1 is not allowed, except when the
same row is selected!
CLK_YL
Clock of YL shift register.
Shifts on rising edge.
Document #: 38-05709 Rev. *A
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