BCM43353LIUBGT Datasheet, PDF (136/143 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/Radio with Integrated Bluetooth 4.1 for Automotive and Industrial Applications

BCM43353 Data Sheet
Power-Up Sequence and Timing
Section 19: Power-Up Sequence and
Timing
Sequencing of Reset and Regulator Control Signals
The BCM43353 has two signals that allow the host to control power consumption by enabling or disabling the
Bluetooth, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are
provided to indicate proper sequencing of the signals for various operational states (see Figure 43, Figure 44
on page 136, and Figure 45 and Figure 46 on page 137). The timing values indicated are minimum required
values; longer delays are also acceptable.
Description of Control Signals
• WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON
input to control the internal BCM43353 regulators. When this pin is high, the regulators are enabled and the
WLAN section is out of reset. When this pin is low the WLAN section is in reset. If both the BT_REG_ON
and WL_REG_ON pins are low, the regulators are disabled.
• BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal BCM43353
regulators. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this
pin is low and WL_REG_ON is high, the BT section is in reset.
Note:
• For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay
between consecutive toggles (where both signals have been driven low). This is to allow time for
the CBUCK regulator to discharge. If this delay is not followed, then there may be a VDDIO in-rush
current on the order of 36 mA during the next PMU cold start.
• The BCM43353 has an internal power-on reset (POR) circuit. The device will be held in reset for
a maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold. Wait at least
150 ms after VDDC and VDDIO are available before initiating SDIO accesses.
• VBAT should not rise 10%–90% faster than 40 microseconds. VBAT should be up before or at the
same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.
• Ensure that BT_REG_ON is driven high at the same time as or before WL_REG_ON is driven high.
BT_REG_ON can be driven low 100 ms after WL_REG_ON goes high.
Broadcom^®
November 14, 2014 • 43353-DS104-R
Page 135