BCM43353LIUBGT Datasheet, PDF (134/143 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/Radio with Integrated Bluetooth 4.1 for Automotive and Industrial Applications

BCM43353 Data Sheet
gSPI Signal Timing
The gSPI host and device always use the rising edge of clock to sample data.
Figure 42: gSPI Timing
SDIO/gSPI Timing
Table 52: gSPI Timing Parameters
Parameter
Symbol Minimum
Maximum
Units Note
Clock period
Clock high/low
T1
T2/T3
20.8
–
ns
(0.45 × T1) – T4 (0.55 × T1) – T4 ns
F_max = 48 MHz
–
Clock rise/fall time^{a T4/T5}
–
2.5
ns Measured from 10% to 90% of
VDDIO
Input setup time T6
5.0
–
ns Setup time, SIMO valid to
SPI_CLK active edge
Input hold time
T7
5.0
–
ns Hold time, SPI_CLK active edge
to SIMO invalid
Output setup time T8
5.0
–
ns Setup time, SOMI valid before
SPI_CLK rising
Output hold time T9
5.0
–
CSX to clock^b
–
7.86
–
Clock to CSX^a
–
–
–
ns Hold time, SPI_CLK active edge
to SOMI invalid
ns CSX fall to 1st rising edge
ns Last falling edge to CSX high
a. Limit applies when SPI_CLK = F_max. For slower clock speeds, longer rise/fall times are acceptable provided that
the transitions are monotonic and the setup and hold time limits are complied with.
b. SPI_CSx remains active for entire duration of gSPI read/write/write-read transaction (overall words for multiple-
word transaction).
Broadcom^®
November 14, 2014 • 43353-DS104-R
Page 133