BCM43353LIUBGT Datasheet, PDF (13/143 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/Radio with Integrated Bluetooth 4.1 for Automotive and Industrial Applications

BCM43353 Data Sheet
List of Figures
List of Figures
Figure 1: Functional Block Diagram................................................................................................................... 2
Figure 2: BCM43353 Block Diagram ............................................................................................................... 19
Figure 3: Typical Power Topology for BCM43353 ........................................................................................... 24
Figure 4: Recommended Oscillator Configuration ........................................................................................... 28
Figure 5: Recommended Circuit to Use with an External Reference Clock..................................................... 29
Figure 6: Startup Signaling Sequence ............................................................................................................. 40
Figure 7: CVSD Decoder Output Waveform Without PLC ............................................................................... 42
Figure 8: CVSD Decoder Output Waveform After Applying PLC..................................................................... 42
Figure 9: Functional Multiplex Data Diagram................................................................................................... 47
Figure 10: PCM Timing Diagram (Short Frame Sync, Master Mode) .............................................................. 48
Figure 11: PCM Timing Diagram (Short Frame Sync, Slave Mode) ................................................................ 49
Figure 12: PCM Timing Diagram (Long Frame Sync, Master Mode)............................................................... 50
Figure 13: PCM Timing Diagram (Long Frame Sync, Slave Mode)................................................................. 51
Figure 14: UART Timing .................................................................................................................................. 52
Figure 15: I²S Transmitter Timing .................................................................................................................... 55
Figure 16: I²S Receiver Timing........................................................................................................................ 55
Figure 17: Broadcom GCI or BT-SIG Mode LTE Coexistence Interface for BCM43353 ................................. 57
Figure 18: Signal Connections to SDIO Host (SD 4-Bit Mode) ........................................................................ 60
Figure 19: Signal Connections to SDIO Host (SD 1-Bit Mode) ........................................................................ 60
Figure 20: Signal Connections to SDIO Host (gSPI Mode) ............................................................................. 61
Figure 21: gSPI Write Protocol ........................................................................................................................ 62
Figure 22: gSPI Read Protocol ........................................................................................................................ 62
Figure 23: gSPI Command Structure............................................................................................................... 63
Figure 24: gSPI Signal Timing Without Status (32-bit Big Endian) .................................................................. 64
Figure 25: gSPI Signal Timing with Status (Response Delay = 0; 32-bit Big Endian) ..................................... 65
Figure 26: WLAN Boot-Up Sequence .............................................................................................................. 68
Figure 27: WLAN MAC Architecture ................................................................................................................ 69
Figure 28: WLAN PHY Block Diagram............................................................................................................. 74
Figure 29: Radio Functional Block Diagram .................................................................................................... 76
Figure 30: 145-Ball WLBGA (Top View) .......................................................................................................... 77
Figure 31: Port Locations for Bluetooth Testing............................................................................................... 96
Figure 32: Port Locations Showing Optional ePA and eLNA (Applies to 2.4 GHz and 5 GHz) ..................... 103
Figure 33: SDIO Bus Timing (Default Mode) ................................................................................................. 124
Figure 34: SDIO Bus Timing (High-Speed Mode).......................................................................................... 126
Figure 35: SDIO Clock Timing (SDR Modes) ................................................................................................ 127
Broadcom^®
November 14, 2014 • 43353-DS104-R
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