SM3G Datasheet, PDF (7/36 Pages) Connor-Winfield Corporation – ULTRA MINIATURE STRATUM 3 MODULE

Detailed Description continued
Furthermore, under register access control, a backup holdover history register is provided. It may be loaded from the active holdover
history or restored to the active holdover history. The active holdover history may also be flushed.
Holdover mode may be entered at any time. If there is no holdover history available, the prior output frequency will be maintained.
When in holdover, the application may read (via register access) the time since holdover was enterred.
Master/Slave Operation
Pairs of SM3G devices may be operated in a master/slave configuration for redundant timing source applications. A typical
configuration is shown below.:
Figure 3
Master / Slave Configuration
REFS1-4
M/S REF
SM3G
1
M/S OUTPUT / OUTPUT1 / BITS
M/S REF
REFS1-4
SM3G
2
M/S OUTPUT / OUTPUT1 / BITS
Any output of each device may be cross-connected to the other device’s M/S Ref input. The device auto-detects the frequency
on the M/S Ref input. Master or slave state of a device is determined by the M/S pin. Thus, master/slave state is always manually
controlled by the application. The master synchronizes to the selected input reference, while the slave synchronizes to the M/S Ref
input. (Note that 8kHz frame phase alignment is maintained across a master/slave pair of devices only if M/S Output is used as the
cross couple signal.)
The unit operating in slave mode locks on and phase-aligns to the cross-reference clock (M/S Output or Output 1) from the unit
in master mode. The phase skew between the input cross-reference and the output clock for the slave unit is typically less than ±1ns
(under ±3ns in dynamic situations, including reference jitter and wander).
Perfect phase alignment of the two Output 1 output clocks would require no delay on the cross-reference clock connection. To
accommodate path length delays, the SM3G provides a programmable phase skew feature. The slave’s Output 1 or M/S Outputmay
be phase shifted -32nS to +31.75nS relative to M/S Input according to the contents of the MS_Phase_Offset register to compensate
for the path length of the M/S Output or Output 1 to M/S Input connection. This offset may therefore be programmed to exactly
compensate for the actual path length delay associated with the particular application’s cross-reference traces. The offset may further
be adjusted to accommodate any output clock distribution path delay differences. Thus, master/slave switches with the SM3G devices
may be accomplished with near-zero phase hits.
The first time a unit becomes a slave, such as immediately after power-up, its output clock phase starts out arbitrary, and will
quickly phase-align to the cross-reference from the master unit. The phase skew will be eliminated (or converged to the programmed
phase offset) step by step. The whole pull-in-and-lock process will complete in about 60 seconds. There is no frequency slew
protection in slave mode. In slave mode, the unit’s mission is to lock to and follow the master.
Once a pair of units has been operating in aligned master/slave mode, and a master/slave switch occurs, the unit that becomes
master will maintain its output clock phase and frequency while a phase build-out (to the current output clock phase) is performed on
its selected reference input. Therefore, as master mode operation commences, there will be no phase or frequency hits on the clock
output.
Likewise, the unit that becomes the slave will maintain its output clock frequency and phase for 1 msec before starting to follow the
cross-reference, protecting the downstream clock users during the switch. Assuming the phase offset is programmed for the actual
propagation delay of this cross-reference path, there will again be no phase hits on the output clock of the unit that has transitioned
from master to slave.
SM3G5 Data Sheet #: TM083 Page 7 of 36 Rev: 05 Date: 01/26/11
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