SM3G Datasheet, PDF (2/36 Pages) Connor-Winfield Corporation – ULTRA MINIATURE STRATUM 3 MODULE

General Description
The SM3G timing module provides a clock output that meets or exceeds Stratum 3 specifications given in GR-1244-CORE (Issue
2), GR-253-CORE (Issue 3), ITU-T G.812 (Type 3) and ITU-T G813 (Option 2).The SM3G features four reference inputs that will
auto-detect the following reference frequencies: 8 kHz, 1.544 MHz, 2.048 MHz, 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84
MHz and 77.76 MHz.
The SM3G timing module can be configured during production to produce an output up to 77.76 MHz. This output is derived from
an onboard VCXO and must be specified when ordering.The BITS output selectable for either 1.544 or 2.048 MHz.The master/slave
output is 8KHz.The user communicates with the SM3G module through a SPI port. The user controls the SM3G operation by writing
to the appropriate registers. The user can also enable or disable SPI operation through a SPI_Enable pin.
The SM3G offers a wide range of options for the system designer.The bandwidth is SPI Port-selectable from 0.025 Hz to 1.6 Hz.
0.098 Hz is the recommended operational bandwidth for SONET Minimum Clock and most Stratum 3 applications.The 8 kHz output
has an adjustable pulse width.The pull-in range is also adjustable to establish the desired reference frequency rejection limits.A
Free Run frequency calibration value can be written to the module to provide a high degree of accuracy in the free run mode.The
reference frequency for any given reference input is automatically detected.A wealth of status information is available through the SPI
Port registers.The user also has a choice between autonomous or full manual control operation.
In manual mode, the user controls the module operating modes Free Run, Hold Over or locked to a specific reference in normal
mode.If the chosen reference is unavailable or disqualified the module automatically enters Hold Over.
In autonomous control mode, operational mode selection occurs automatically based on reference priority and qualification status.
When the active reference becomes disqualified, the module will switch to another qualified reference. If none is available, it will switch
to Holdover. In the revertive mode the module will seek to acquire the highest priority qualified reference.In the non-revertive mode
the module will not return to the previous reference even after it is re-qualified unless there are no other qualified references.
Switching between references is hitless.Likewise, the output frequency slew rate is minimized during any change of operating
mode, including entry into and return from Free Run or Hold Over to protect traffic from transient-induced bit errors.
Reference Status information and the operating mode information is accessed through status registers.The module will set the
Interrupt pin (SPI_INT) low to indicate a status change.An Alarm pin is used to indicate failure of the active reference status.
Free Run operation guarantees an output within 4.6ppm of nominal frequency and Holdover operation guarantees the output
frequency will not change by more than 0.37ppm during the first 24 hours.Frequency accuracy is based on a TCXO for its small size,
low power consumption and outstanding performance over all environmental conditions.
The module operates on 3.3V ± 5% with a typical power draw of less than 500 milliwatts. The module operates over the 0° to 70° C
commercial temperature range.
Figure 1
Functional Block Diagram
TRST
TCK
TDO
TDI
TMS
M/S REF
4
REF 1 - 4
RESET
MASTER SELECT
T1/E1
SPI_ENBL
SPI_CLK
SPI_IN
SPI_OUT
SPI_INT
OCXO
EEPROM
DAC
VCXO
Reference Input Monitor
Control
Mode
Reference
Selection
Reference Priority,
Revertivity and Mask
Table
DPLL
Bus Interface
APLL
OUTPUT1
M/S_OUT
BITS_CLK
LOS
LOL
HOLD_GOOD
SM3G5 Data Sheet #: TM083 Page 2 of 36 Rev: 05 Date: 01/26/11
© Copyright 2011 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice