SM3G Datasheet, PDF (6/36 Pages) Connor-Winfield Corporation – ULTRA MINIATURE STRATUM 3 MODULE

Detailed Description
The SM3G can accept up to 4 external references from 8 kHz to 77.76 MHz and each is monitored for signal presence and
frequency offset. Additionally, a cross-couple reference input is provided for master/slave operation. Reference selection may be
manual or automatic, according to pre-programmed priorities. All reference switches are performed in a hitless manner, and frequency
ramp controls ensure smooth output signal transitions. When references are switched, the device provides an automatic phase build-
out to minimize phase transitions in the output clocks.
Three output signals are provided, the first up to 77.76 MHz , the second fixed at 8 kHz for use as a Frame Sync signal as well as a
cross-couple reference for master/slave operation.The third output is a BITS clock, selectable as either 1.544 MHz or 2.048 MHz.
Device operation may be in Free Run, locked, or Hold Over modes. In Free Run, the clock frequencies are simply determined by
the accuracy of the calibrated internal clock. In locked mode, the SM3G phase locks to the selected input reference. While locked, a
frequency history is accumulated. In Hold Over mode, theoutput frequencies are generated according to this history.
The Digital Phase Locked Loop provides the critical filtering and frequency/phase control that meet or exceed all requirements in
critical jitter and accuracy performance parameters. Filter bandwidth may be configured to suit applications requirements.
Control functions are provided via standard SPI bus register interface. Register access provides visibility into a variety of registered
information as well as providing extensive programmable control capability.
Operating Modes: The SM3G Operates in Either Free Run, Locked, or Hold Over Mode:
Free Run – In Free Run mode, Output 1, M/S Output, and BITS_Clk, the output clocks, are determined directly from and
have the accuracy of the calibrated free running internal clock. Reference inputs continue to be monitored for signal presence and
frequency offset, but are not used to synchronize the outputs.
Locked – The Output 1, M/S Output, and BITS_Clk, outputs are phase locked and track the selected input reference. Upon
entering the Locked mode, the device begins an acquisition process that includes reference qualification and frequency slew rate
limiting, if needed. Once satisfactory lock is achieved, the “Locked” bit is set in the DPLL_Status register, and a compilation of the
frequency history of the selected reference is started.When a usable Hold Over history has been established, the Hold_Good pin is
set, and the “Hold Over Available” bit is set in the DPLL_Status register.
Phase comparison and phase lock loop filtering operations in the SM3G are completely digital. As a result, device and loop
behavior are entirely predictable, repeatable, and extremely accurate. Carefully designed and proven algorithms and techniques
ensure completely hit-less reference switches, operational mode changes, and master/slave switches.
Basic loop bandwidth is programmable from .025 Hz to 1.6 Hz, giving the user a wide range of control over the system response.
When a new reference is acquired, maximum frequency slew limits ensure smooth frequency changes. Once lock is achieved,
(<100 seconds for stratum 3), the “Locked” bit is set. If the SM3G is unable to maintain lock, Loss of Lock (LOL) is asserted. All
transitions between locked, Hold Over and Free Run modes are performed with minimal phase events and smooth frequency and
phase transitions.
Reference phase hits or phase differences encountered when switching references (or when entering locked mode) are nulled out
with an automatic phase build-out function, with a residual phase error of less than 1ns.
Hold Over – Upon entering Hold Over mode, the Output 1, M/S Output, and BITS_Clk, outputs are determined from the Hold
Over history established for the last selected reference. Output frequency is determined by a weighted average of the Hold Over
history, and accuracy is determined by the internal clock. Hold Over mode may be entered manually or automatically. Automatic entry
into Hold Over mode occurs when operating in the automatic mode, the reference is lost, and no other valid reference exists. The
transfer into and out of Hold Over mode is designed to be smooth and free of hits. The frequency slew is also limited to a maximum of
±2 ppm/sec.
The history accumulation algorithm uses a first order frequency difference filtering algorithm. Typical holdover accumulation takes
about 15 minutes. When a usable holdover history has been established, the Hold_Good pin is set, and the “Holdover Available” bit is
set in the DPLL_Status register. The holdover history continues to be updated after “Holdover Avaialble” is declared.
The algorithm accumulates the holdover history only when it has locked to either an external reference in Master operation or the
M/S REF clock in Slave operation, starting 15 minutes after power up. Tracking will be suspended automatically when switching to a
new reference and in Hold Over or Free Run mode. A set of registers allows the application to control a holdover history maintenance
policy, enabling either a re-build or continuance of the history when a reference switch occurs.
SM3G5 Data Sheet #: TM083 Page 6 of 36 Rev: 05 Date: 01/26/11
© Copyright 2011 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice