SM3G Datasheet, PDF(25/36 Page) Connor-Winfield Corporation

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SM3G Datasheet, PDF (25/36 Pages) Connor-Winfield Corporation – ULTRA MINIATURE STRATUM 3 MODULE

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Application Notes

Available Output1 frequencies are: 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz or 77.76MHz. After the module is

powered up, pull the reset pin low for 10ms.Wait 1200ms and read the contents of register 0x33.If it reads 1 then the module came

up properly.If it reads 0 then reset the module and re-read register0c33 after 1200ms.The contents of 0x33 must read 1 before using

the module.

Reference Inputs â The application may supply up to 4 reference inputs, applied at input pins Ref1 - 4. They may each be 8

kHz, 1.544 MHz, 2.048 MHz, 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz or 77.76 MHz. The device auto-detects the

reference frequencies, and they may be read from the Ref(1-4)_Frq_Priority registers in register control mode, as described in the

control mode sections that follow.

Reference switches are performed in a hitless manner.However, if the application externally changes the frequency of a particular

reference, the device requires 20ms to auto-detect the new frequency.Manual switches to a frequency changed reference should not

be made during this interval.Automatic reference selection mode accounts for the auto-detection in the reference qualification.

References would typically (but need not be) connected in decreasing order of usage priority. For example if redundant BITS clocks

are available, they would typically be assigned to Ref1 and Ref2, with other transmission derived signals following thereafter.

Master/Slave operation â For some applications, reliability requirements may demand that the clock system be duplicated. The

SM3G device will support the master/slave duplicated configuration for such applications. To facilitate itâs use, the device includes the

necessary signal cross coupling and control functions. Redundancy for reliability implies two major considerations: 1) Maintaining

separate failure groups such that a failure in one group does not affect itâs mate, and 2) Physical and logical partitioning for repair,

such that a failed component can be replaced while the mate remains in service, if so desired. System design needs to account to

meet system level goals.

Figure 8

REF1

REF4

Master / Slave Configuration

REF1

SM3G

RESF4TC3B5IT0S0_CLK

OUTPUT1

M/S_OUT

M/S REF

BITS clock output

Synchronized clock output

8 kHz

M/S REF

REF1

M/S_OUT

OUTPUT1

BITS_CLK

SM3G

REF4

8 kHz

Synchronized clock output

BITS clock output

SM3G5 Data Sheet #: TM083 Page 25 of 36 Rev: 05 Date: 01/26/11

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