SM3G Datasheet, PDF (15/36 Pages) Connor-Winfield Corporation – ULTRA MINIATURE STRATUM 3 MODULE

Register Descriptions and Operation continued
Phase_Offset, 0x0e (R/W)
Bit 7 ~ Bit 0
The 2’s complement value of phase offset between Master Output module and Slave Output module, ranges from -32 nS to +31.75 nS
Positive Value: Master Output rising edge leads Slave Output
Negative Value: Master Output rising edge lags Slave Output
In slave mode, the slave’s outputs may be phase shifted -32nS to +31.75nS in .25nS increments, relative to the Mas-
ter module according to the contents of the Phase_Offset register, to compensate for the path length of the Master to
Slave connection.
If a phase offset is used, then the two SM3G devices would typically be written to the appropriate phase offset val-
ues for the respective path lengths of each Master to Slave connection, to ensure that the same relative output signal
phases will persist through master/slave switches.
Calibration, 0x0f (R/W)
Bit 7 ~ Bit 0
2’s complement value of local oscillator digital calibration in 0.05 ppm resolution
To digitally calibrate the free running clock synthesized from the internal clock, this register is written with a value cor-
responding to the known frequency offset of the oscillator from the nominal center frequency.
Fr_Pulse_Width, 0x10 (R/W)
Bit 7 ~ Bit4
Bit 3 ~ Bit 0
Reserved
Pulse width for M/Sclock output,
1-15 multiples of the Sync_Clk clock period.
BITS 4 and 5 of the Ctl_Mode register determine if the M/S 8 kHz output is 50% duty cycle or pulsed (high going)
outputs. When they are pulsed, the Fr_Pulse_Width register determines the width. Width is the register value multiple of
the Sync_Clk clock period. Valid values are 1 - 15.
Reset default is 0001. Writing to 0000 maps to 0001.
DPLL_Status, 0x11 (R)
Bit 7 ~Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Hold Over
Build
Complete
1: Complete
0: Incomplete
Hold Over
Available
1: Avail.
0: Not avail.
Locked
1: Locked
0: Not locked
Loss of Lock
1: Loss of Lock
0: No loss of lock
Loss of Signal
1: No activity
on active
reference
0: Active ref-
erence signal
present
Bit 0 indicates the presence of a signal on the selected reference.
Bit 1 indicates a loss of lock (LOL). Loss of lock will be asserted if lock is not achieved within the specified time for the
stratum level of operation, or lock is lost after being established previously. LOL will not be asserted for automatic refer-
ence switches.
Bit 2 indicates successful phase lock. It will typically be set in <100 seconds for stratum 3 with a good reference. It will
indicate “not locked” if lock is lost.
Bit 3 indicates if a Hold Over history is available.
Bit 4 indicates when a new Hold Over history has been sucessfully built and transferred to the active Hold Over history.
*NOTE: Only references 1 - 4 are used with this model
SM3G5 Data Sheet #: TM083 Page 15 of 36 Rev: 05 Date: 01/26/11
© Copyright 2011 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice