SM3G Datasheet, PDF (12/36 Pages) Connor-Winfield Corporation – ULTRA MINIATURE STRATUM 3 MODULE

Register Descriptions and Operation
Chip_ID_low, 0x00 (R)
Low byte of chip ID: 0x12
Bit 7 ~ Bit 0
Chip_ID_High, 0x01 (R)
High byte of chip ID: 0x30
Bit 7 ~ Bit 0
Chip_Revision, 0x02 (R)
Chip revision number: 0x05
Bit 7 ~ Bit 0
Bandwidth, 0x03 (R/W)
Bit 7 ~ Bit 5
Bit 4
Bit 3 ~ Bit 0
Reserved
Reserved
0:Default
Bandwidth Selection in Hz:
0000: 0.025
0001: 0.025
0010: 0.025
0011: 0.025
0100: 0.025
0101: 0.025
0110: 0.049
0111: 0.098(Reset Default)
1000: 0.20
1001: 0.39
1010: 0.78
1011 - 1111: 1.6
BITS 3 - 0 select the phase lock loop bandwidth in Hertz. The reset default is 0.098 Hz.
Ctl_Mode, 0x04 (R/W)
Bit 7 ~ Bit 6 Bit 5
Reserved
Default: 0
Bit 4
M/S Output
Pulse width
control:
0: 50%
1: Controlled by
FR_Pulse_Width
register
Default: 0
Bit 3
BITS Clock
Output
Frequency:
1: 1.544 MHz
0: 2.048 MHz
(read only)
Bit 2
HM Ref:
0: Register control
of op mode/ref
(Will always
be 0)
Bit 1
Active
Reference
Selection:
1: Manual
0: Automatic
Default: 1
Bit 0
Reserved
When bit 1 is reset (automatic reference and mode selection), Bits 3 - 0 of the Op_Mode register become read-only.
The power-up default for Bit 1 = 1 for manual reference selection and default for Bit 4 = 0 for 50% duty cycle on M/S
Output.
When the device is in slave mode, it will lock to the M/S REF, independent of the values written to BITS 3 - 0 of the
Op_mode register. The operational mode and reference selection written to Bits 3 - 0 while in slave mode will, however,
take effect when the device is made the master.
When bit 1 of the Ctl_Mode register is reset (automatic reference and mode selection) and the device is in master
mode, BITS 3 - 0 of the Op_Mode register become read-only.
SM3G5 Data Sheet #: TM083 Page 12 of 36 Rev: 05 Date: 01/26/11
© Copyright 2011 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice