SM3G Datasheet, PDF (16/36 Pages) Connor-Winfield Corporation – ULTRA MINIATURE STRATUM 3 MODULE

Register Descriptions and Operation continued
Intr_Event, 0x12 (R)
Bit 7
Loss of
Lock
Bit 6
Loss of
Signal
Bit 5
Active refer-
ence change
Bit 4
DPLL Mode
status
change
Bit 3
M/S Ref
Change from
no activity to
activity
Bit 2
M/S Ref
Change from
activity to no
activity
Bit 1
Any refer-
erence change
from not
available to
available
Bit 0
Any refer-
erence change
from available
able to not
available
Interrupt state = 1. When an enabled interrupt occurs, the SPI_INT pin is asserted, active low. All interrupts are cleared
and the SPI_INT pin pulled high when the register is read. Reset default is 0.
Intr_Enable, 0x13 (R/W)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Enable Inter- Enable Inter-
rupt event 7: rupt event 6:
1: Enable 1: Enable
0: Disable 0: Disable
Default: 0 Default: 0
Enable Inter-
rupt event 5:
1: Enable
0: Disable
Default: 0
Enable Inter-
rupt event 4:
1: Enable
0: Disable
Default: 0
Enable Inter-
rupt event 3:
1: Enable
0: Disable
Default: 0
Enable Inter-
rupt event 2:
1: Enable
0: Disable
Default: 0
Enable Inter- Enable Inter-
rupt event 1: rupt event 0:
1: Enable 1: Enable
0: Disable 0: Disable
Default: 0 Default: 0
Enables or disables the corresponding interrupts from asserting the SPI_INT pin. Interrupt events still appear in the
Intr_Event register independent of their “enable” state. Reset default is interrupts disabled.
Ref(1-4)_Frq_Offset, 0x14 ~ 0x17(R)
Bit 7 ~ Bit 0
2’s complement value of frequency offset between reference and calibrated local oscillator, 0.2ppm resolution
These registers indicate the frequency offset, in 0.2ppm resolution, between each reference and the local calibrated
oscillator. 0x14 - 0x17 correspond to Ref1 - Ref4.
Ref(1-4)_Frq_Priority, 0x1c ~ 0x1f (R/W)
Bit 7 ~ Bit 4
Bit 3
Bit 2 ~ Bit 0
Frequency
0000: None
0001: 8 kHz
0010: 1.544 MHz
0011: 2.048 MHz
0100: 12.96 MHz
0101: 19.44 MHz
0110: 25.92 MHz
0111: 38.88 MHz
1000: 51.84 MHz
1001: 77.76 MHz
1010-1111: Reserved
Revertivity
1: revertive
0: non-revertive
Default: 0,
non revertive
Priority
0: highest
3: lowest
Default: 0
BITS 2 - 0 indicate the priority of each reference for use in automatic reference selection mode (bit 1 of the Ctl_Mode
register =0). In manual reference selection mode (bit 1 of the Ctl_Mode register = 1), these BITS are read-only and will
contain either the reset default or values written when last in automatic reference selection mode. For equal priority
values, lower reference numbers have higher priority.
Bit 3 specifies if the reference is revertive or non-revertive in automatic reference selection mode. When a reference
fails, the next highest priority “available” (signal present, non-masked, and acceptable frequency offset) reference will
be selected. When a reference returns, it will be switched to only if it is of higher priority and the current active reference
is marked “Revertive”.
BITS 7 - 4 indicate the auto-detected frequency for each reference. Invalid frequencies may result in erroneous
device operation. If there is no activity on a reference, bits 7-4will be = 0000. Bits 7-4 are read only. 0x1c - 0x1f
correspond to Ref1 - Ref4.
SM3G5 Data Sheet #: TM083 Page 16 of 36 Rev: 05 Date: 01/26/11
© Copyright 2011 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice