STC5425 Datasheet, PDF (6/48 Pages) Connor-Winfield Corporation – Line Card Clock

STC5425 Pin Description
STC5425
Line Card Clock
Data sheet
All I/O is LVCMOS, except for CLK1 is LVPECL/LVDS. REF4 and REF5 are LVCMOS/LVPECL/LVDS.
Table 1: Pin Description
Pin Name
AVCC
AGND
VCC
GND
TRST
TCK
TMS
TDI
TDO
RST
MCLK
EVENT_INTR
EX_SYNC1
EX_SYNC2
EX_SYNC3
REF1
REF2
REF3
REF4_P
REF4_N
REF5_P
REF5_N
CLK1_P
CLK1_N
CLK2
Pin #
4,14
3,15
8, 9, 12,
22, 32,
36, 38,
39, 45,
46, 54,
57
1, 7, 10,
11, 21,
31, 40,
53, 58
37
49
41
51
50
48
6
5
28
33
35
29
30
34
23
24
25
26
19
20
56
I/O
3.3V analog power input
Analog ground
3.3V digital power input
Description
Digital ground
I JTAG boundary scan reset, active low
I JTAG boundary scan clock
I JTAG boundary scan mode selection
I JTAG boundary scan data input
O JTAG boundary scan data output
I Active low to reset the chip
I Master clock input (TCXO or XO)
O Event interrupt
I Frame Sync signal 1
I Frame Sync signal 2
I Frame Sync signal 3
I Reference input 1
I Reference input 2
I Reference input 3
I Differential reference input 4 (LVPECL/LVDS)
I Differential reference input 4 (LVPECL/LVDS)
I Differential reference input 5 (LVPECL/LVDS)
I Differential reference input 5 (LVPECL/LVDS)
O Clock output CLK1 positive. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₁
LVPECL or LVDS
O Clock output CLK1 negative, 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₁
LVPECL or LVDS
O Clock output CLK2 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₃, proprietary
composite signal of Synthesizer F or Synthesizer G_T4 (T4). LVCMOS.
Preliminary
Page 6 of 48 TM113
Rev:P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 20, 2011