STC5425 Datasheet, PDF(14/48 Page) Connor-Winfield Corporation

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STC5425 Datasheet, PDF (14/48 Pages) Connor-Winfield Corporation – Line Card Clock

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STC5425

Line Card Clock

Data sheet

General Description

Application

The STC5425 is a single chip line card solution for

applications in SONET, SDH, and Synchronous

Ethernet network elements. Its highly integrated

design implements all necessary reference selection,

monitoring, filtering, synthesis, and control functions.

An external oscillator (e.g., stable TCXO or XO) com-

pletes a system level solution (see Functional Block

Diagram, Figure 1). The STC5425 has four options

for frequency of external oscillator.

Overview

The STC5425 accepts 5 reference inputs and gener-

ates 4 synchronized clock outputs, including 2 frame

pulse clock outputs at 8kHz and 2kHz. One PLL-

based timing generator provide the essential func-

tions for frequency translation of reference input to a

line card clock. It controls synthesizers G1, G4, and

synthesizer F. Clock outputs CLK1 and CLK2 can be

derived from synthesizer G1 and G4, respectively.

Frame pulse clock outputs are derived from synthe-

sizer F. The STC5425 incorporates a SPI interface,

providing access to status registers.

most appropriate one from the reference inputs

according to the reFveurtnivcittyiosntaatulsS, paendcifeiaccahtiroenfer-

enceâs priority and qualification. Revertivity deter-

mines whether a higher priority qualified reference

should preempt a qualified current selected refer-

ence. If none of the references input is qualified, hold-

over or freerun mode will be elected depending on

the availability of the holdover history.

Reference selection may be automatic, manual, or

hard-wired manual. In automatic reference selection

mode, the most appropriate one elected from the auto

reference elector will be the selected reference input.

In manual reference selection mode, user may spec-

ify any of the reference inputs as the selected refer-

ence input for external timing or holdover/freerun for

self-timing. In hard-wired manual mode, user can

hard-wired switch using control pin SRCSW between

two pre-programmed reference inputs. The reference

input elected from the auto reference elector will not

affect the selected reference input in manual or man-

ual mode.

External Frame Sync Inputs

The STC5425 has three external frame sync inputs at

2kHz or 8kHz on the pin EX_SYNC1, EX_SYNC2,

EX_SYNC3, respectively. The frequency of the exter-

nal frame sync inputs are auto-detected.

Chip Master Clock

The STC5425 operates with an external oscillator

(e.g., TCXO or XO) as its master clock. The device

supports four different frequencies of master clock:

10MHz, 12.8MHz, 19.2MHz, and 20MHz. Initial

default accepted frequency is 12.8MHz.

Reference Inputs and External

Sync Inputs

The STC5425 accepts 5 reference inputs. 3 LVCMOS

and 2 LVPECL/LVDS/LVCMOS. The 5 reference

inputs are continuously activity and quality monitored.

The reference inputs may be selected to accept either

the auto-detect acceptable reference frequency which

can be automatically detected by STC5425 or manu-

ally acceptable reference frequency. The activity

monitoring is implemented with a programmable

leaky bucket algorithm. A reference is designated as

âqualifiedâ if it is active and its fractional frequency off-

set is within the programmed range for a programmed

soaking time. An auto reference elector elects the

To achieve frame phase alignment, any one of the

three external sync inputs may be selected as frame

reference for selected REF1 to REF5 individually.

Timing Generators and Operation

Modes

The STC5425 includes one timing generator. It can

individually operate in Freerun, Synchronized, and

Holdover mode. The timing generator is in either

external-timing mode or self-timing mode. In external

timing mode, PLL of the timing generator phase locks

to the selected external reference input. In self-timing

mode, the PLL simply tunes the clock synthesizers to

a given fractional frequency offset. Synchronization is

in external timing mode. PLLâs loop bandwidth may

be programmed to vary the timing generatorâs filtering

function. Conversely, freerun and holdover are all in

self-timing mode. When selected reference input and

previous holdover history are unavailable, such as in

systemâs initialization stage, freerun mode may be

entered or used. When selected reference input is

Preliminary

Page 14 of 48 TM113 Rev: P1.3

Date: September 20, 2011

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