STC5425 Datasheet, PDF (21/48 Pages) Connor-Winfield Corporation – Line Card Clock

STC5425
Line Card Clock
Data sheet
Clock Outputs Details
The STC5425 generates 1 synchronized differential
(LVPECL or LVDS) clock output: CLK1; 3 LVCMOS
clock outputs: CLK2, one 8kHz and one 2kHz frame
pulse clock outputs. Figure 5, Figure 6, and Figure 7
respectively shows the clock output section for CLK1,
CLK2, and CLK8K/CLK2K. Each output has individ-
ual clock output section consist of synthesizer and
clock generator. Clock generator of CLK1 has
LVPECL/LVDS driver to produce differential output.
Clock generators of CLK2 include a mux and a LVC-
MOS signal driver. Clock generator of frame output
CLK8K and CLK2K consist of a duty cycle controller
and a LVCMOS driver.
Synthesizer F
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Duty Cycle _LVCMOS
CLK8K
Controller _Driver
8kHz frame pulse
CLK2K Generator
Duty Cycle _LVCMOS
Controller _Driver
CLK2K
2kHz frame pulse
Figure 7:Output Clocks CLK8K and CLK2K
Clock Output Phase Alignment
Any of clock outputs which has frequency at the inte-
ger multiple of 8kHz is in phase alignment with the
frame pulse output CLK8K if none of synthesizer
skew is programmed.
Clock Synthesizers
The STC5425 has 3 clock synthesizers: synthesizer
G1, G4 and one frame pulse clock synthesizer F;
Clock synthesizers G₁ and G₄ produce frequencies
from 1MHz to 156.25MHz, in 1kHz steps. Phase
skew of these synthesizers are all programmable
individually up and down 50ns. CLK1 is derived from
synthesizer G₁. CLK2 can be derived from synthe-
sizer G₄. Synthesizer F produces frame pulse at 8kHz
and 2kHz with 50% duty cycle or programmable pulse
width.
Clock Generators
Clock generator of CLK1 consist of a LVPECL/LVDS
signal driver. The signal level of clock outputs CLK1
can be programmed to either LVPECL or LVDS.
Clock generators of CLK2 consist of a LVCMOS
driver. CLK2 is LVCMOS. Signal level is driven from
LVCMOS driver in clock generator. The clock genera-
tor of frame pulse output CLK8K and CLK2K contains
a duty cycle controller and a LVCMOS driver. The
duty cycle is programmable at the register CLK8K
Sel and CLK2K Sel.
Synthesizer G₁
CLK1 Generator
LVPECL
/LVDS
DRIVER
CLK1
1MHz ~ 156.25MHz
Figure 5:Output Clocks CLK1
Synthesizer Skew Programming
The STC5425 allows user to program the phase skew
of each clock synthesizer, up and down 50ns in
roughly 0.024ns steps. Since each of clock outputs is
dedicate derived from its synthesizer respectively,
adjust phase skew of the synthesizer will provide the
associated clock output a phase skew adjustment.
Phase skew of the synthesizers may be programmed
at the register Synth Skew Adj.
Clock Outputs
Available frequencies of CLK1 and CLK2 are from
1MHz to 156.25MHz, in 1kHz steps. Phase skew is
adjustable at the associate synthesizer level. Two
clock outputs, CLK8K and CLK2K, generate two
frame pulse clock at 8kHz and 2kHz.
Event Interrupts
The STC5425 events shown following below are
interrupt events might occurred.
- Qualification status of the reference inputs change
- Activity status of the cross reference inputs change
- Selected reference of timing generator changes in auto-
matic reference selection
- PLL status of timing generator changes
- Out-Event of timing generator asserts
Synthesizer G₄
CLK2 Generator
LVCMOS
DRIVER
CLK2
1MHz ~ 156.25MHz
Figure 6:Output Clocks CLK2
The interrupt events can be read from the register
Interrupt Status. Each bit indicates one events. The
associate bit of the register Interrupt Status will not
be changed automatically when the event is cleared.
Therefore, the user need write ‘1’ to the associate bit
to erase the event.
Preliminary
Page 21 of 48 TM113 Rev: P1.3
Date: September 20, 2011
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice