STC5425 Datasheet, PDF (16/48 Pages) Connor-Winfield Corporation – Line Card Clock

STC5425
Line Card Clock
Data sheet
Detailed Description
The STC5425 is a single chip solution for line card
application in SDH, SONET, and Synchronous Ether-
net network elements. The revolutionary pure-digital
internal modules, DSP-based PLL and clock synthe-
sizer are used in the device so that the overall char-
acteristics are more stable compared to ones in
traditional method.
Operation Mode
Functional Specification
The STC5425 includes a timing generator that has a
PLL individually operate in either external-timing or
self-timing mode. In external timing mode, PLL of a
timing generator phase-locks to a reference input. In
self-timing mode, PLL simply operates with the exter-
nal oscillator (MCLK). The STC5425 supports three
operation modes: freerun (self-timing), synchronized
(external-timing), and holdover (self-timing).
Chip Master Clock
The STC5425 operates with an external oscillator
(e.g., TCXO or XO) as its master clock on the pin
MCLK. Generally, user should select an oscillator has
great stability and low phase noise as the master
clock (MCLK).
The device supports four different accepted frequen-
cies of master clock: 10MHz, 12.8MHz, 19.2MHz,
and 20MHz. Initial default accepted frequency of
MCLK for STC5425 is 12.8MHz. When 10MHz,
19.2MHz, or 20MHz is selected as the frequency of
MCLK, the user must write register MCLK Freq
Reset three times consecutively, with no intervening
read/writes from/to other register. An internal soft-
reset will occur after three writes completed. The
accepted frequency of MCLK input returns to
12.8MHz following any regular reset. See register
MCLK Freq Reset for details.
In the meantime, the STC5425 allows user to read
three values at the register MCLK Freq Reset:
FRQID, COUNT, and ID Written Value.
FRQID
Indicates the ID of the frequency of MCLK that the
STC5425 currently accept.
COUNT
Indicates how many times the register MCLK Freq
Reset has been written to.
ID Written Value
Indicates the ID of associated value that is being writ-
ten to the register MCLK Freq Reset.
See the register MCLK Freq Reset for more details.
Freerun Mode
Freerun mode is typically used during system’s initial-
ization stage when none of reference inputs is avail-
able and the clock synchronization has not been
achieved. The clock output generated from the
STC5425 in freerun mode is relative to the internal
freerun clock which is synthesized from MCLK. Fre-
quency of the internal freerun clock can be calibrated
by writing to the register Freerun Cali.
Synchronized Mode
In synchronized mode, the built-in PLL of the timing
generator locks to the selected reference input. Each
timing generator’s loop bandwidth is independently
programmable from 13Hz to 100Hz by writing to the
register Loop Bandwidth. The noise transfer func-
tion of the PLL is determined according to the loop
bandwidth and has maximum gain under 0.2dB. In
synchronized mode, the phase relationship between
the reference input and the clock output can be con-
figured as arbitrary or aligned at register Frame
Phase Align.
Holdover Mode
When none of reference inputs is available, holdover
mode is used to maintain the frequency offset of the
clock output closely to previous value generated
when the selected reference input was valid. In hold-
over mode, the clock output is synthesized from the
MCLK along with device holdover history which is
acquired from the short-term holdover history. Short
term holdover history is accumulated by a built in pro-
grammable short-term history accumulator consecu-
tively, which indicate the latest updated fractional
frequency offset of the synchronous clock output. The
bandwidth of the accumulator may be configured at
the register Short Term History Bandwidth. The
user can read the short-term history from register
Short Term Accu History.
Preliminary
Page 16 of 48 TM113 Rev: P1.3
Date: September 20, 2011
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice