STC5425 Datasheet, PDF (30/48 Pages) Connor-Winfield Corporation – Line Card Clock

Interrupt_Event_Enable, 0x1B (R/W)
Address
Bit7
Bit6
Bit5
0x1B
Not used
STC5425
Line Card Clock
Data sheet
Bit4
Event 4
Bit3
Event 3
Bit2
Event 2
Bit1
Not used
Bit0
Event 0
Event 0
Event 1
Event 2
Event 3
Event 4
Reference qualification status changed
Reserved
Selected reference changed in auto selection mode
PLL status changed
Timing generator’s out-event occurred
Selects which of events will assert the pin EVENT_INTR to active mode (See register Interrupt_Config).
0 = mask out, 1 = enable
Default value: 0
Interrupt_Config, 0x1C (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x1C
Not used
Idle mode
Signal active
state
Signal active state
Specify the signal active state at pin EVENT_INTR
0 = active low. 1 = active high
Idle mode
Specify the state of pin EVENT_INTR when no interrupt event occurs.
0 = tri-state. 1 = logic inactive
Default value: 0
Hard-wired_Switch_Pre_Selection, 0x1D (R/W)
Address
0x1D
Bit7
Bit6
Bit5
Bit4
Pre-selected reference number 2
Bit3
Bit2
Bit1
Bit0
Pre-selected reference number 1
Pre select reference number 1 and reference number 2 in hard-wired manual reference selection mode. This
mode is controlled by pin SRCSW. When pin SRCSW is LOW, reference number 1 is pre-selected. When pin
SRCSW is HIGH, reference number 2 is pre-selected. It only can be configured when bit7 of Control_Mode
register is set to 1 (See register Control_Mode).
Field Value
0
1~5
13
14,15
Selection
Freerun
Ref1~Ref5
Holdover
Reserved
Preliminary
Page 30 of 48 TM113
Rev:P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 20, 2011