STC5425 Datasheet, PDF (38/48 Pages) Connor-Winfield Corporation – Line Card Clock

STC5425
Line Card Clock
Data sheet
Phase skew adjust for synthesizers based on which synthesizer index is selected at the register
Synth_Index_Select. See description of the register Synth_Index_Select. The adjustment is from -6400/128
ns to 6396.875/128 ns, which is -50ns ~ 49.976 ns, in 3.125/128 ns steps, 2’s complement.
Default value: 0 (For all the synthesizers)
CLK1_Signal_Level 0x50 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
0x50
Not used
Selects the signal level for clock outputs CLK1
0 = LVPECL, 1 = LVDS
Default value: 0
CLK1_Sel, 0x51(R/W)
Bit1
Bit0
CLK1 Signal Level
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
0x51
Not used
Selects clock output CLK1 derived from synthesizer G₁ or put in tri-state.
Bit1
Bit0
CLK1 Synthesizer Select
Default value: 0
CLK2_Sel, 0x52 (R/W)
Bits 1 ~ 0
0, 2, 3
1
CLK1 Synthesizer Select
Put CLK1 in tri-state mode
Synthesizer G₁
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x52
Not used
CLK2 Synthesizer Select
Selects the clock output CLK2 derived from synthesizer G₄. Signal level of CLK2 is LVCMOS.
Default value: 0
Bits 1 ~ 0
0, 2, 3
1
CLK3 Synthesizer Select
Put CLK2 in tri-state mode
Synthesizer G₄
Preliminary
Page 38 of 48 TM113
Rev:P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 20, 2011