STC5425 Datasheet, PDF (17/48 Pages) Connor-Winfield Corporation – Line Card Clock

STC5425
Line Card Clock
Data sheet
PLL Event In
The STC5425 provides direct communication with the
PLL’s timing generator by writing to the register PLL
Event In. Following events can be triggered:
- Relock. PLL starts a relock process if this event is trig-
gered. In frame phase align mode, PLL relocks to the ref-
erence input and the frame edge is re-selected as well.
In phase arbitrary mode, PLL relocks to the reference
input and restart the phase rebuild process.
Frame Phase Relationship
In synchronized mode, the phase relationship
between the reference input and the clock output can
be programmed to frame phase arbitrary or frame
phase align.
Frame Phase Arbitrary
If phase arbitrary is selected, phase relationship
between clock output and reference input is non-zero
fixed value. Frame phase arbitrary incorporates
phase rebuild function on reference input switching or
mode switching. Hit-less switching is achieved with
phase rebuild function and the impact on downstream
is minimized. Frame phase arbitrary is enabled at the
register Frame Phase Align.
Frame Phase Align
If frame phase align is selected, the clock output has
zero frame phase relationship with the selected refer-
ence input. The STC5425 may accept external frame
reference and select frame edge to achieve frame
phase alignment for REF1 ~ REF5 individually. Both
external frame reference and frame edge are
selected at the register Frame Phase Align.
History of Fractional Frequency
Offset
The STC5425 monitors and tracks the fractional fre-
quency offset between the clock output and MCLK.
The history data of the frequency offset is used by
clock synthesizers to generate desire outputs while
the timing generator is pending for reference input
availability. A weighted 3^rd order low-pass filter is
used internally as short term history accumulators. A
mature short term history is stored and further
updated as device holdover history. It is used when
the STC5425 operates in holdover mode.
Short-Term History
Short-term history i^Fs^uaⁿn^ctaⁱv^oeⁿra^ag^le^Spfre^eq^cuⁱe^fin^cc^ay^tio^offⁿset
between the clock output and MCLK which is filtered
internally using a weighted 3rd order low-pass filter
with the small time constant. The -3dB filter response
point can be programmed from 0.16Hz to 1.3Hz by
writing to the register Short Term History Band-
width. Short- term history can be read from the regis-
ter Short Term Accu History. Typically, short-term
history is used by clock synthesizer in two conditions:
First, it is used in between the transition of two differ-
ent operation modes; second, it is used if LOS occurs
when the STC5425 operates in synchronized mode
with manually reference selection.In addition, short-
term history is provided to perform failure diagnostics
and evaluations.
Device Holdover History
Device holdover history is the history data used when
the STC5425 runs in holdover mode. It is acquired
from the short term history previously described. In
synchronized mode, when timing generators PLL has
locked to the selected reference input, the short term
history is stored and further updated as the device
holdover history. If LOS or LOL occurs, the device
holdover history will stay at the latest updated value
until re-enter the synchronized mode and the PLL
locks to the replaced selected reference input. Its
value can be read from the register Device Holdover
History.
Phase-Locked Loop Status Details
The register PLL Status contains the detailed status
of the PLLs, including the signal activity of the
selected reference, the synchronization status, and
the availability of the holdover histories.
SYNC bit
In external-timing mode, this bit indicates the
achievement of synchronization. This bit will not be
asserted in self-timing mode.
LOS bit
In external-timing mode, this bit indicates the loss of
signal on the selected reference. This bit will not be
asserted in self-timing mode.
LOL bit
In external-timing mode, the bit will be set if the PLL
fails to achieve or maintain lock to the selected refer-
ence. This bit will not be asserted in self-timing mode.
Preliminary
Page 17 of 48 TM113 Rev: P1.3
Date: September 20, 2011
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice