CDB4923 Datasheet, PDF (7/50 Pages) Cirrus Logic – Evaluation Board

CDB4923 CDB49300
age regulators on the board (U8 and U27) which
are used to power the DSP and the I/O pads of the
PLD (U11). The +12 V and -12 V supplies are used
to power the input buffers on the analog side of the
board.
The power section of the CDB4923/300 can be
found in Figure 5. The CDB4923/300 requires a
+5 V input on J23 and a digital ground connected
to J24 in order to power the digital section of the
board. The analog portion requires a +12 V supply
on binding post J21, -12 V on J57, and analog
ground connected to J22.
2.2 Dolby^ Considerations
It should be noted by the system designer that addi-
tional circuitry may be required in order to obtain
Dolby Certification (e.g., analog bass manage-
ment). System requirements are dependent upon
the nature of the end product and which group of
Dolby Certification is required. The designer
should consult the Dolby Licensee Information
Manual and contact Dolby Laboratories to deter-
mine exactly what is required to meet Dolby spec-
ifications for a particular system.
3. DIGITAL SIGNAL PROCESSOR
The CS492x/CS493xx (U1) must be downloaded
with application code and configured for operation
each time that it is powered up. Each time the de-
coder needs to be reconfigured, the host must send
hardware configuration and application configura-
tion messages to the DSP. A complete description
of the software applications and their messaging
protocol can be found in application notes AN120-
AN123, AN140 for the CS492x and AN161-
AN163 for the CS493xx.
Please note that this document and all other docu-
mentation pertaining to the CS492x family of de-
coders can be found at the following website:
http://www.cirrus.com/products/overviews/cs4923.html
This document and all other documentation per-
taining to the CS493xx family of decoders can be
found at the following website:
http://www.cirrus.com/products/overviews/cs49300.html
As the focus of the board, the CS492x/CS493xx
performs all processing of digital audio. The DSP
section of the board is illustrated in Figure 4. The
CS492x/CS493xx can be fed compressed data or
linear PCM from various sources. However, it
should be noted that each load of application soft-
ware for the DSP is designed to process a specific
data type, e.g. DTS^ application code does not
process linear PCM. Please reference the appropri-
ate software application note (i.e. AN120-AN123,
AN140 or AN161-AN163) to determine which
hardware configurations and audio data types are
supported.
3.1 Control Signals
The host interface to the DSP, which allows code
download and other communication, can be access-
ed through the parallel port interface (J29) or by
placing the control PLD into an external interface
mode. In the external interface mode the user can
drive the signal pins of the DSP by tapping into the
signals present on headers J11 and J12. More infor-
mation on selecting the host control mode can be
found in Data Selection.
The host interface mode of the DSP is selected at
the rising edge of reset and is programmable. The
communication mode is determined by the states of
the RD, WR, and PSEL pins when the DSP comes
out of reset, as described in the CS4923/4/5/6/7/8/9
datasheet and the CS49300 datasheet. Each mode is
described in the CS4923/4/5/6/7/8/9 Hardware Us-
er’s Guide (AN115) and the CS49300 datasheet.
There are six jumpers used to directly control the
CS492x/CS493xx. Jumpers J2 (WR), J3 (RD), and
J62 (PSEL) are used to select the host interface
mode for the CS492x/CS493xx. Table 1 lists the
jumper settings required for all four host interface
modes. Note that the CDB4923/300 requires
DS262DB2
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