CDB4923 Datasheet, PDF (44/50 Pages) Cirrus Logic – Evaluation Board

CDB4923 CDB49300
header can be used to probe signals during normal operation, and may be used as a wirewrap
point when using Data Selection Mode 0 or 1, as detailed in the Data Selection section of this
datasheet.
J12
Stake header providing access to all serial audio data and clock pins. This header can be used
to probe signals during normal operation, and may be used as a wirewrap point when using
Data Selection Mode 0 or 1, as detailed in the Data Selection section of this datasheet
J62
This jumper selects the pull-up/pull-down state of the CS492x/CS493xx’s PSEL pin. When
coming out of reset, the state of the PSEL pin determines which parallel interface mode to use
(Motorola or Intel) when initializing the CS492x/CS493xx into a parallel host interface mode.
This jumper is used in conjunction with J2 and J3 to select the Host Interface Mode of the
CS492x/CS493xx when it comes out of reset. Because the PSEL pin has multiplexed function-
ality it also serves as SCDIO when in I²C mode. By default this jumper is in the ’HI’ position since
the board is initially configured for I²C serial communication and the SCDIO pin is open-drained.
The settings for J2 (WR), J3 (RD) and J62 (PSEL) are detailed in the CS4923/4/5/6/7/8/9
datasheet and the CS49300 datasheet.
Default: HI
14.4
POWER JUMPERS
J59
This jumper connects DSP_PWR to the analog side of the CS492x/CS493xx. Analog current con-
sumption can be measured by removing this jumper and connecting an ammeter in series with the
jumper.
Default: INSTALLED
J60
This jumper connects DSP_PWR to the digital side of the CS492x/CS493xx. Digital current
consumption can be measured by removing this jumper and connecting an ammeter in series
with the jumper.
Default: INSTALLED
J63
This jumper is used to select the maximum voltage at which the I/O pins of the system PLD
(U11) will drive its outputs. The user can select between +3.3 V and +2.5 V.
Default: +3.3 V
J69
This jumper (DSP_PWR) is used to select the core voltage for DSP power. This jumper is pro-
vided to allow the user to evaluate both the CS4923/4/5/6/7/8 family and the CS49300 family of
audio decoders. The CS4923/4/5/6/7/8 family requires +3.3 V, while the CS49300 family re-
quires +2.5 V. The user can select between +3.3 V and +2.5 V.
CDB4923 Default: +3.3 V
CDB49300 Default: +2.5 V
14.5
SYSTEM CLOCKING JUMPERS
J37
This dual position jumper select between an oscillator or the MK2744-10S discrete PLL (U26)
as the external clock source for the DSP of the CS492x/CS493xx, and it also selects the system
MCLK for non-S/PDIF input modes. It is important to note the jumpers of J37 must move togeth-
er. They must be both in the ’OSC’ position or they must both be in the ’PLL’ position. Moving
only one jumper will result in erratic behavior.
When both jumpers are in the ’OSC’ position, the CS492x/CS493xx CLKIN pin is driven by the
oscillator, Y1, and some of the data modes chosen by switch S3 will provide a system MCLK
which is also derived from Y1. Specifically, all data selection modes listed in Table 9 and Table
24 showing an MCLK Source of ’OSC/PLL’ will generate a system MCLK equal to the frequency
of the oscillator Y1.
If you have questions about how to utilize the external PLL, please contact the factory before
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DS262DB2