CDB4923 Datasheet, PDF(14/50 Page) Cirrus Logic

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CDB4923 Datasheet, PDF (14/50 Pages) Cirrus Logic – Evaluation Board

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CDB4923 CDB49300

6. CLOCKING

There are four major clocks routed across the

CDB4923/300: CLKIN for the DSP, MCLK, LR-

CLK, and SCLK. CLKIN is only used to drive the

digital logic of the DSP core. MCLK, LRCLK, and

SCLK are used for synchronizing the audio sys-

tems of the CDB4923/300.

6.1 DSP Clock

The DSP clock of the CS492x/CS493xx is provid-

ed at the CLKIN pin (pin 30). The setting of jumper

J1 (DSP CLOCK) determines whether the

CS492x/CS493xx uses the input clock as the DSP

clock directly (CLKIN position) or uses the input

clock as a reference for the internal PLL (PLL po-

sition).

There are two possible clock sources on the

CDB4923/300. The first is the OSCILLATOR

(Y1). The second option is the external PLL (U26)

which can be configured to provide a processor

clock ranging from 33 MHz to 81 MHz. All clock-

ing circuitry can be found in Figure 8.

Since the PLL (U26) and the OSCILLATOR (Y1)

are co-dependent, only one can be used at any giv-

en time. Jumper J37 is used to select the source of

the main DSP clock. It is vital to note that the jump-

er J37 is a double jumper with two jumpers which

must be moved in unison. If the jumpers are not

moved together, board behavior will be unpredict-

able. Table 11 lists the oscillator requirements, and

the two different settings for J37, where pins 3 and

4 are connected to the inputs of the PLD. Jumper

J37 can also be found in Figure 8.

In order to use the 27 MHz oscillator directly, Y1

should be populated with the 27 MHz oscillator in-

cluded with the CDB4923/300 package. Addition-

Clock

Source

Oscillator

External

PLL

J37 - Pin 3 J37 - Pin 4

27 MHz or

12.288 MHz

oscillator

27 MHz

oscillator

OSC

PLL

OSC

PLL

Table 11. Board Clocking Configurations (J37)

PLD

Mode

DATA

SEL2

DATA

SEL1

DATA

SEL0

CS492X/CS493XX

CMPDAT

CS492X/CS493XX

SDATAN1

Data and Control lines accessed via J11 and J12

S/PDIF -- CS8414

A/D -- CS5334

S/PDIF -- CS8414

A/D -- CS5334

RESERVED

MCLK

MASTER

J12 or DSP

CS8414

DSP

CS8414

OSC/PLL

CONTROL

SOURCE

J11 & J12

Table 9. Data Selection Modes (Switch S3, PLD Version AB-X)

PLD

Mode

DATA_SEL2

DATA_SEL1

DATA_SEL0

CS492x/CS493xx

CMPDAT

J12

S/PDIF â CS8414

CS492x/CS493xx

SDATAN1

J12

A/D -- CS5334

Table 10. EXTERNAL Data Selection Modes (PLD Version AB-X)

MCLK

SOURCE

J12 or DSP

CS8414

DS262DB2

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