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CDB4923 Datasheet, PDF (43/50 Pages) Cirrus Logic – Evaluation Board
CDB4923 CDB49300
14. APPENDIX H: JUMPERS LISTED BY FUNCTION
14.1
AUDIO INPUT JUMPERS
J31
This jumper is used to select the input connector which is being used to receive S/PDIF data.
Placing the jumper in the ’RCA’ position enables the RCA jack, and placing the jumper in the
’OPT’ position enables the TORX173 optical receiver.
Default: OPT
J52
This jumper is used to control the MASTER/SLAVE clocking mode of the CS5334 as described
in the CS5334 datasheet. This jumper should be left in the ’SLAVE’ position when using the fac-
tory programmed PLD provided with the CDB4923/300.
Default: SLAVE
J65
This jumper is used to control the SEL pin of the CS8414. This pin, in conjunction with J66, is
used to select which channel status pin information to display on the status output pins. Please
refer to the CS8414 datasheet for more details on how to configure the CS8414.
Default: HI (Not Populated).
J66
This jumper is used to control the CS12/FCK pin of the CS8414. This pin, in conjunction with
J65, is used to select which channel status pin information to display on the status output pins.
Please refer to the CS8414 datasheet for more details on how to configure the CS8414.
Default: HI (Not Populated).
14.2
AUDIO OUTPUT JUMPERS
J44
This particular component is actually a set of jumpers. Each individual jumper can be used to
control the state of one channel status bit in the outgoing S/PDIF stream created by the
CS8404A. More details can be found in the datasheet for the CS8404A and the specifications
for IEC60958 and IEC61937 bitstreams.
Default: All bits HI {Not Populated}
14.3
DSP JUMPERS
J1
This jumper is used to control the internal clocking of the CS492x/CS493xx. When in the
’CLKIN’ position, the CS492x/CS493xx uses the clock on the CLKIN pin to drive the DSP core
directly. When in the ’PLL’ position, the CS492x/CS493xx derives all internal clocks from the
reference frequency provided at the CLKIN pin.
Default: CLKIN
J2
This jumper selects the pull-up/pull-down state of the CS492x/CS493xx’s WR pin. This jumper
is used in conjunction with J3 and J62 to select the Host Interface Mode of the
CS492x/CS493xx when it comes out of reset. By default the CDB4923/300 is configured for I2C
serial communication. The settings for J2 (WR), J3 (RD) and J62 (PSEL) are detailed in the
CS4923/4/5/6/7/8/9 datasheet and the CS49300 datasheet.
Default: HI
J3
This jumper selects the pull-up/pull-down state of the CS492x/CS493xx’s RD pin. This jumper
is used in conjunction with J2 and J62 to select the Host Interface Mode of the
CS492x/CS493xx when it comes out of reset. By default the CDB4923/300 is configured for I2C
serial communication. The settings for J2 (WR), J3 (RD) and J62 (PSEL) are detailed in the
CS4923/4/5/6/7/8/9 datasheet and the CS49300 datasheet.
Default: LO
J11
Stake header providing some serial communication lines, and all general purpose I/O pins. This
header is also serves as the memory interface to the CRD4923_MEM/CDB49300_MEM. This
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