CDB4923 Datasheet, PDF (45/50 Pages) Cirrus Logic – Evaluation Board

CDB4923 CDB49300
adjusting this jumper. Y1 must be a 27 MHz oscillator before attempting to use U26. When
both jumpers are in the ’PLL’ position, U26 will drive the CLKIN pin of the CS492x/CS493xx with
the configured PCLK (refer to Table 12 or Table 22), and the system MCLK will be driven by
ACLK. The frequency of MCLK can be programmed by changing the values of the AS1 and AS0
pins of U26 as detailed in Table 13 of this datasheet.
Default: OSC OSC
J67
Jumper used to set the value of the PS1 pin of U26. This jumper, in conjunction with J68 and
J72, determines the processor clock frequency provided by the external PLL. Please refer to
Table 12 or Table 22 for more details.
Default: LO
J68
Jumper used to set the values of the PS0 pin of U26. This jumper, in conjunction with J67 and
J72, determines the processor clock frequency provided by the external PLL. Please refer to
Table 12 or Table 22 for more details.
Default: HI
J70
Jumper used to set the values of the AS1 pin of U26. This jumper, in conjunction with J71, de-
termines the MCLK frequency provided by the external PLL. Please refer to Table 13 for more
details.
Default: HI
J71
Jumper used to set the values of the AS0 pin of U26. This jumper, in conjunction with J70, de-
termines the MCLK frequency provided by the external PLL. Please refer to Table 13 for more
details.
Default: 50
J72
Jumper used to set the values of the PS2 pin of U26. This jumper, in conjunction with J67 and
J68, determines the processor clock frequency provided by the external PLL. Please refer to
Table 12 or Table 22 for more details.
Default: LO
DS262DB2
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