CS42325 Datasheet, PDF (52/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC with Headphone

6.8 DAC2 Clocking (Address 08h)
7
Reserved
6
DAC2_MCLK
5
Reserved
4
DAC2_SP
3
Reserved
CS42325
2
Reserved
1
0
DAC2_DIF1 DAC2_DIF0
6.8.1
DAC2 MCLK Source
This bit selects which MCLK pin provides the clock for DAC2.
DAC2_MCLK
0
1
MCLK1
MCLK2
DAC2 MCLK source
6.8.2
DAC2 Serial Port Source
This bit selects which serial port provides the sub clocks for the DAC2.
DAC2_SP
0
1
Serial Port 1 (SCLK1/LRCK1)
Serial Port 2 (SCLK2/LRCK2)
DAC2 sub clock source
6.8.3
DAC2 Digital Interface Format (DAC2_DIF)
These bits configure the serial audio interface format for incoming digital audio data on SDIN2.
DAC2_DIF[1:0]
00
01
10
11
DAC2 Serial Audio Interface Format
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right Justified, 16-bit data
Right Justified, 24-bit data
6.9 ADC Control (Address 0Ah)
7
Reserved
6
5
ADC_HPFRZ ADC_SOFT
4
Reserved
3
Reserved
2
AIN_SEL2
1
AIN_SEL1
0
AIN_SEL0
6.9.1
ADC High-Pass Filter Freeze
The high-pass filter works by continuously subtracting a measure of the DC offset from the output of the
decimation filter. If the ADC_HPFRZ bit is taken high during normal operation, the current value of the DC
offset is frozen and this DC offset will continue to be subtracted from the conversion result. For DC mea-
surements, this bit must be set to ‘1’.
6.9.2
ADC_HPFRZ
0
1
Continuous DC Subtraction
Fixed DC Subtraction
ADC High-Pass Filter Freeze
ADC Soft Ramp Control
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
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