CS42325 Datasheet, PDF (31/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC with Headphone

4.2.3
CS42325
ADC, DAC1, and DAC2 clock selection
The ADC, DAC1, and DAC2 can be independently set to use either of the two serial ports as a clock
source. Each also has control over which MCLK to use. This allows for full flexibility in configuration of the
converter. Master/Slave control is achieved at the serial port level (See Figure 9 on page 29); the internal
converters discussed here are always slave.
Each converter has a bit in the registers (xxx_SP, where xxx = ADC, DAC1, or DAC2) which allows se-
lection of the SCLK/LRCK pair used for the converter. The xxx_MCLK bits select which MCLK source to
use for the converter. If the serial port selected for use is in master mode, this selection must be the same
as the MCLK_SPx for the serial port which is in use. In Slave mode the MCLK selected must be synchro-
nous to the LRCK/SCLK selected by xxx_SP.
ADC_MCLK
DAC1_MCLK
DAC2_MCLK
Internal-MCLK1
Internal-MCLK2
Internal-LRCK1
Internal-LRCK2
Internal-SCLK1
Internal-SCLK2
0
1
ADC_SP
0
1
0
1
ADC
Internal-MCLK1
Internal-MCLK2
Internal-LRCK1
Internal-LRCK2
Internal-SCLK1
Internal-SCLK2
0
1
DAC1_SP
0
1
0
1
DAC1
Internal-MCLK1
Internal-MCLK2
Internal-LRCK1
Internal-LRCK2
Internal-SCLK1
Internal-SCLK2
0
1
DAC2_SP
0
1
0
1
DAC2
ADC_DIF[2:0]
SDOUT
DAC1_DIF[2:0]
SDIN1
DAC2_DIF[2:0]
SDIN2
Figure 11. Converter Clocking
4.2.4
High-Impedance Digital Output
Each serial port may be placed on a clock/data bus that allows multiple masters, without the need for ex-
ternal buffers. The 3ST_SP1, 3ST_SP2 and 3ST_SDOUT bits place the internal buffers for the serial port
signals in a high-impedance state, allowing another device to transmit clocks or data without bus conten-
tion.
CS42324
Transmitting Device #1
Transmitting Device #2
3ST_SDOUT
SDOUT
3ST_SPx
SCLKx/LRCKx
Receiving Device
Figure 12. Tri-State Serial Port
DS838A2
31