CS42325 Datasheet, PDF (4/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC with Headphone

CS42325
4.5.2.1 Recommended Power-Up Sequence, Hardware Mode ............................................. 38
4.5.2.2 Recommended Power-Down Sequence, Hardware Mode ........................................ 38
4.5.3 Software Mode Start-Up ........................................................................................................ 38
4.5.3.1 Recommended Power-Up Sequence, Software Mode .............................................. 38
4.5.3.2 Recommended Power-Down Sequence, Software Mode ......................................... 38
4.5.4 Initialization Flow Chart ......................................................................................................... 39
4.6 Device Control ................................................................................................................................ 40
4.6.1 Hardware Mode ..................................................................................................................... 40
4.6.2 Software Mode - I²C Control Port .......................................................................................... 41
4.6.3 Software Mode - SPI Control Port ......................................................................................... 42
4.6.3.1 SPI Write .................................................................................................................... 42
4.6.3.2 SPI Read ................................................................................................................... 42
4.6.4 Memory Address Pointer (MAP) ............................................................................................ 43
4.6.4.1 Map Increment (INCR) ............................................................................................... 43
4.7 Interrupts and Overflow .................................................................................................................. 43
5. REGISTER QUICK REFERENCE ........................................................................................................ 44
6. REGISTER DESCRIPTION .................................................................................................................. 46
6.1 Device I.D. and Revision Register (Address 00h) (Read Only) ...................................................... 46
6.1.1 Device I.D. (Read Only) ........................................................................................................ 46
6.1.2 Chip Revision (Read Only) .................................................................................................... 46
6.2 Mute Control (Address 01h) ........................................................................................................... 46
6.2.1 System MCLK Source ........................................................................................................... 46
6.2.2 Mute DAC2 Left-Channel ...................................................................................................... 46
6.2.3 Mute DAC2 Right-Channel .................................................................................................... 47
6.2.4 Mute DAC1 Left-Channel ...................................................................................................... 47
6.2.5 Mute DAC1 Right-Channel .................................................................................................... 47
6.2.6 Mute ADC Left-Channel ........................................................................................................ 47
6.2.7 Mute ADC Right-Channel ...................................................................................................... 47
6.3 Operational Control (Address 02h) ................................................................................................. 47
6.3.1 Global Power-Down .............................................................................................................. 47
6.3.2 INT Pin High/Low Active (INT_H/L) ....................................................................................... 48
6.3.3 Freeze ................................................................................................................................... 48
6.3.4 Tri-State SDOUT ................................................................................................................... 48
6.3.5 Tri-State Serial Port 1 ............................................................................................................ 48
6.3.6 Tri-State Serial Port 2 ............................................................................................................ 49
6.4 Serial Port 1 Control (Address 03h) ................................................................................................ 49
6.4.1 Serial Port 1 Master/Slave Select .......................................................................................... 49
6.4.2 Serial Port 1 Speed Mode ..................................................................................................... 49
6.4.3 MCLK1 Divider ...................................................................................................................... 49
6.4.4 Serial Port 1 MCLK source .................................................................................................... 49
6.5 Serial Port 2 Control (Address 04h) ................................................................................................ 50
6.5.1 Serial Port 2 Master/Slave Select .......................................................................................... 50
6.5.2 Serial Port 2 Speed Mode ..................................................................................................... 50
6.5.3 MCLK2 Divider ...................................................................................................................... 50
6.5.4 Serial Port 2 MCLK Source ................................................................................................... 50
6.6 ADC Clocking (Address 06h) .......................................................................................................... 50
6.6.1 ADC MCLK Source ............................................................................................................... 50
6.6.2 ADC Serial Port Source ......................................................................................................... 51
6.6.3 ADC Digital Interface Format (ADC_DIF) .............................................................................. 51
6.7 DAC1 Clocking (Address 07h) ........................................................................................................ 51
6.7.1 DAC1 MCLK Source ............................................................................................................. 51
6.7.2 DAC1 Serial Port Source ....................................................................................................... 51
6.7.3 DAC1 Digital Interface Format (DAC1_DIF) .......................................................................... 51
6.8 DAC2 Clocking (Address 08h) ........................................................................................................ 52
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DS838A2