CS42325 Datasheet, PDF (50/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC with Headphone

6.5 Serial Port 2 Control (Address 04h)
7
6
5
4
SP2_M/S
Reserved Reserved0 SP2_SPEED
3
MCLK2
FREQ1
CS42325
2
MCLK2
FREQ0
1
Reserved
0
SP2_MCLK
6.5.1
Serial Port 2 Master/Slave Select
This bit configures Serial Port 2 to operate as either a clock master or clock slave.
6.5.2
SP2_M/S
0
1
Slave Mode
Master Mode
Serial Port 2 Master/Slave Select
Serial Port 2 Speed Mode
In Master Mode this bit configures the speed mode of Serial Port 2.
6.5.3
SP2_SPEED
0
1
Single-Speed Mode (SSM)
Double-Speed Mode (DSM)
Serial Port 2 Speed Mode
MCLK2 Divider
These bits configure the internal MCLK2 dividers.
6.5.4
MCLK2
FREQ[1:0]
00
÷1
01
÷1.5
10
÷2
11
÷3
MCLK Divider
Serial Port 2 MCLK Source
This bit selects which MCLK pin provides the clock for deriving Master Mode sub-clocks for Serial Port 2.
SP2_MCLK
0
1
MCLK1
MCLK2
Serial Port 2 MCLK source
6.6 ADC Clocking (Address 06h)
7
Reserved
6
ADC_MCLK
5
Reserved
4
ADC_SP
3
Reserved
2
Reserved
1
ADC_DIF1
0
ADC_DIF0
6.6.1
ADC MCLK Source
This bit selects which MCLK pin provides the clock for the ADC.
ADC_MCLK
0
1
MCLK1
MCLK2
ADC MCLK source
50
DS838A2