CS42325 Datasheet, PDF (22/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC with Headphone

CS42325
SWITCHING CHARACTERISTICS - SERIAL AUDIO
Logic ‘0’ = GND = GNDH = 0 V; Logic ‘1’ = VL; C_L = 20 pF.
Parameter
Master Clock (MCLKx = MCLK1, MCLK2)
MCLKx Frequency
MCLKx Duty Cycle
Sample Rates
Single-Speed Mode
Double-Speed Mode
Master Mode
SCLKx Frequency
SCLKx Period
1/(128*108 kHz)
SCLKx Duty Cycle (Note 18)
LRCKx setup
LRCKx hold
before SCLK rising
after SCLK rising
SDOUT setup
SDOUT hold
before SCLK rising
after SCLK rising
Slave Mode
SCLKx Frequency (Note 19)
SCLKx Period
SCLKx Duty Cycle
LRCKx setup
LRCKx hold
SDOUT setup
SDOUT hold
1/(128•108 kHz)
before SCLK rising
after SCLK rising
before SCLK rising
after SCLK rising
Symbol
-
-
t_PERIOD
t_HIGH ÷ t_PERIOD
t_SETUP1
t_HOLD1
t_SETUP2
t_HOLD2
-
t_PERIOD
t_HIGH ÷ t_PERIOD
t_SETUP1
t_HOLD1
t_SETUP2
t_HOLD2
Min
1.024
40
4
50
64•Fs
72.3
40
20
20
10
10
-
72.3
40
20
20
10
10
Typ
Max
Unit
-
41.4720 MHz
50
60
%
-
54
108
kHz
-
64•Fs
Hz
-
-
ns
50
60
%
-
-
ns
-
-
ns
64•Fs
-
Hz
-
-
ns
50
60
%
-
-
ns
-
-
ns
Notes: 18. Duty cycle of generated SCLKx in Master Mode depends on duty cycle of the corresponding MCLKx as
specified under “System Clocking” on page 28.
19. In Slave Mode, the SCLK/LRCK ratio can be set according to preference. However, specified perfor-
mance is guaranteed only when using the ratios in Section 4.2.1 Master Mode on page 30 and Section
4.2.2 Slave Mode on page 30.
SCLKx
LRCKx
t_HOLD1
channel
t_PERIOD
t_SETUP1
channel
t_HIGH
SDOUT
data
t_SETUP2
data
t_HOLD2
Figure 3. Serial Input Timing
22
DS838A2