CS42325 Datasheet, PDF (39/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC with Headphone

4.5.4 Initialization Flow Chart
No Power
1. No audio signal
generated.
Power Applied
Off Mode (Power Applied)
1. No audio signal generated.
2. Control Port Registers reset
to default.
CS42325
PDN bit = '1'b?
No
Standby Mode
1. No audio signal generated.
Yes 2. Control Port Registers retain
settings.
3. Update Control Port Registers
as Required.
20 ms delay
Power Off Transition
1. Audible pops.
RST = Low? ^Yes
No
Yes
No
Pull-up on SDOUT?
Hardware Mode
Minimal feature
set support.
Software Mode
Registers setup to
desired settings.
Charge Caps
1. VCMADC/VCMDAC
Charged to quiescent voltage.
2. Filt+/VBIAS Charged.
DAC / ADC
Initialization
2048 internal
MCLKx cycle delay
Digital/Analog
Output Muted
Sub-Clocks Applied
1. LRCKx valid.
2. SCLKx valid.
3. Audio samples
processed .
20 μs delay (DAC
only)
Stand-By
Transition
1. Pops suppressed.
Reset Transition
1. Pops suppressed.
ERROR: Power removed
No
Valid
MCLKx/LRCKx
Ratio?
Yes
RST = Low
ERROR: MCLKx/LRCKx ratio change
Normal Operation
Audio signal generated per control port or stand-
alone settings.
PDN bit set to '1'b
(software mode only)
ERROR: MCLKx removed
Analog Output Freeze
1. AOUTx bias = last audio sample.
2. DAC Modulators stop operation.
3. Audible pops.
Figure 19. Initialization Flow Chart
DS838A2
39