EP7311 Datasheet, PDF (44/54 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE

EP7311
High-Performance, Low-Power System on Chip
Table V. 256-Ball PBGA Ball Listing (Continued)
Ball Location
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
J1
J2
J3
J4
J5
J6
Name
SDCKE
DD[3]
A[1]
D[6]
VSSRTC
BATOK
nBATCHG
VSSIO
D[11]
VDDIO
PB[1]
VDDIO
TDO
PB[4]
PB[6]
VSSRTC
VSSRTC
DD[0]
D[3]
VSSRTC
A[7]
A[8]
A[9]
VSSIO
D[12]
D[13]
PA[7]
PA[5]
VSSIO
PA[4]
PA[6]
PB[0]
PB[2]
VSSRTC
VSSRTC
A[10]
A[11]
A[12]
A[13]/DRA[14]
VSSIO
D[14]
D[15]
PA[3]
PA[1]
VSSIO
PA[2]
PA[0]
TXD[1]
Type
Description
O
SDRAM clock enable output
O
LCD serial display data
O
System byte address
I/O
Data I/O
RTC ground Real time clock ground
I
Battery ok input
I
Battery changed sense input
Pad ground I/O ground
I/O
Data I/O
Pad power Digital I/O power, 3.3V
I
GPIO port B
Pad power Digital I/O power, 3.3V
O
JTAG data out
I
GPIO port B
I
GPIO port B
Core ground Real time clock ground
RTC ground Real time clock ground
O
LCD serial display data
I/O
Data I/O
RTC ground Real time clock ground
O
System byte address
O
System byte address
O
System byte address
Pad ground I/O ground
I/O
Data I/O
I/O
Data I/O
I
GPIO port A
I
GPIO port A
Pad ground I/O ground
I
GPIO port A
I
GPIO port A
I
GPIO port B
I
GPIO port B
RTC ground Real time clock ground
RTC ground Real time clock ground
O
System byte address
O
System byte address
O
System byte address
O
System byte address / SDRAM address
Pad ground I/O ground
I/O
Data I/O
I/O
Data I/O
I
GPIO port A
I
GPIO port A
Pad ground I/O ground
I
GPIO port A
I
GPIO port A
O
UART 1 transmit data out
Table V. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Type
Description
J7
CTS
I
UART 1 clear to send input
J8
VSSRTC
RTC ground Real time clock ground
J9
VSSRTC
RTC ground Real time clock ground
J10
A[17]/DRA[10]
O
System byte address / SDRAM address
J11
A[16]/DRA[11]
O
System byte address / SDRAM address
J12
A[15]/DRA[12]
O
System byte address / SDRAM address
J13
A[14]/DRA[13]
O
System byte address / SDRAM address
J14
nTRST
I
JTAG async reset input
J15
D[16]
I/O
Data I/O
J16
D[17]
I/O
Data I/O
K1
LEDDRV
O
IR LED drivet
K2
PHDIN
I
Photodiode input
K3
VSSIO
Pad ground I/O ground
K4
DCD
I
UART 1 data carrier detect
K5
nTEST[1]
I
Test mode select input
K6
EINT[3]
I
External interrupt
K7
VSSRTC
RTC ground Real time clock ground
K8
ADCIN
I
SSI1 ADC serial input
K9
COL[4]
O
Keyboard scanner column drive
K10
TCLK
I
JTAG clock
K11
D[20]
I/O
Data I/O
K12
D[19]
I/O
Data I/O
K13
D[18]
I/O
Data I/O
K14
VSSIO
Pad ground I/O ground
K15
VDDIO
Pad power Digital I/O power, 3.3V
K16
VDDIO
Pad power Digital I/O power, 3.3V
L1
RXD[1]
I
UART 1 receive data input
L2
DSR
I
UART 1 data set ready input
L3
VDDIO
Pad power Digital I/O power, 3.3V
L4
nEINT[1]
I
External interrupt input
L5
PE[2]/CLKSEL
I
GPIO port E / clock input mode select
L6
VSSRTC
RTC ground Real time clock ground
L7
PD[0]/LEDFLSH
I/O
GPIO port D / LED blinker output
L8
VSSRTC
Core ground Real time clock ground
L9
COL[6]
O
Keyboard scanner column drive
L10
D[31]
I/O
Data I/O
L11
VSSRTC
RTC ground Real time clock ground
L12
A[22]/DRA[5]
O
System byte address / SDRAM address
L13
A[21]/DRA[6]
O
System byte address / SDRAM address
L14
VSSIO
Pad ground I/O ground
L15
A[18]/DRA[9]
O
System byte address / SDRAM address
L16
A[19]/DRA[8]
O
System byte address / SDRAM address
M1
nTEST[0]
I
Test mode select input
M2
nEINT[2]
I
External interrupt input
M3
VDDIO
Pad power Digital I/O power, 3.3V
M4
PE[0]/BOOTSEL[0]
I
GPIO port E / Boot mode select
M5
TMS
I
JTAG mode select
M6
VDDIO
Pad power Digital I/O power, 3.3V
44
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