EP7311 Datasheet, PDF (43/54 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE

EP7311
High-Performance, Low-Power System on Chip
256-Ball PBGA Ball Listing
The list is ordered by ball location.
Table V. 256-Ball PBGA Ball Listing
Ball Location
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
Name
VDDIO
nCS[4]
nCS[1]
SDCLK
SDQM[3]
DD[1]
M
VDDIO
D[0]
D[2]
A[3]
VDDIO
A[6]
MOSCOUT
VDDOSC
VSSIO
nCS[5]
VDDIO
nCS[3]
nMOE/nSDCAS
VDDIO
nSDCS[1]
DD[2]
CL[1]
VDDCORE
D[1]
A[2]
A[4]
A[5]
WAKEUP
VDDIO
nURESET
VDDIO
EXPCLK
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
Type
Description
Pad power Digital I/O power, 3.3V
O
Chip select out
O
Chip select out
O
SDRAM clock out
O
SDRAM byte lane mask
O
LCD serial display data
O
LCD AC bias drive
Pad power Digital I/O power, 3.3V
I/O
Data I/O
I/O
Data I/O
O
System byte address
Pad power Digital I/O power, 3.3V
O
System byte address
O
Main oscillator out
Oscillator
power
Oscillator power in, 2.5V
Pad ground I/O ground
O
Chip select out
Pad power I/O ground
O
Chip select out
O
ROM, expansion OP enable/SDRAM
CAS control signal
Pad power Digital I/O power, 3.3V
O
SDRAM chip select out
O
LCD serial display data
O
LCD line clock
Core power Digital core power, 2.5V
I/O
Data I/O
O
System byte address
O
System byte address
O
System byte address
I
System wake up input
Pad power Digital I/O power, 3.3V
I
User reset input
Pad power Digital I/O power, 3.3V
I
Expansion clock input
Pad ground I/O ground
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Table V. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Type
Description
C12
VDDIO
Pad power Digital I/O power, 3.3V
C13
VSSIO
Pad ground I/O ground
C14
VSSIO
Pad ground I/O ground
C15
nPOR
I
Power-on reset input
C16
nEXTPWR
I
External power supply sense input
D1
WRITE/nSDRAS
O
Transfer direction / SDRAM RAS signal
output
D2
EXPRDY
I
Expansion port ready input
D3
VSSIO
Pad ground I/O ground
D4
VDDIO
Pad power Digital I/O power, 3.3V
D5
nCS[2]
O
Chip select out
D6
nMWE/nSDWE
O
ROM, expansion write enable/ SDRAM
write enable control signal
D7
nSDCS[0]
O
SDRAM chip select out
D8
CL[2]
O
LCD pixel clock out
D9
VSSRTC
Core ground Real time clock ground
D10
D[4]
I/O
Data I/O
D11
nPWRFL
I
Power fail sense input
D12
MOSCIN
I
Main oscillator input
D13
VDDIO
Pad power Digital I/O power, 3.3V
D14
VSSIO
Pad ground I/O ground
D15
D[7]
I/O
Data I/O
D16
D[8]
I/O
Data I/O
E1
RXD[2]
I
UART 2 receive data input
E2
PB[7]
I
GPIO port B
E3
TDI
I
JTAG data input
E4
WORD
O
Word access select output
E5
VSSIO
Pad ground I/O ground
E6
nCS[0]
O
Chip select out
E7
SDQM[2]
O
SDRAM byte lane mask
E8
FRM
O
LCD frame synchronization pulse
E9
A[0]
O
System byte address
E10
D[5]
I/O
Data I/O
E11
VSSOSC
Oscillator
ground
PLL ground
E12
VSSIO
Pad ground I/O ground
E13
nMEDCHG/nBROM
I
Media change interrupt input / internal
ROM boot enable
E14
VDDIO
Pad power Digital I/O power, 3.3V
E15
D[9]
I/O
Data I/O
E16
D[10]
I/O
Data I/O
F1
PB[5]
I
GPIO port B
F2
PB[3]
I
GPIO port B
F3
VSSIO
Pad ground I/O ground
F4
TXD[2]
O
UART 2 transmit data output
F5
RUN/CLKEN
O
Run output / clock enable output
F6
VSSIO
Pad ground I/O ground
DS506PP1
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(All Rights Reserved)
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